Taiwan Semiconductor Manufacturing Comp. Ltd.

Wen-Ju Preet Yang

Chin-Chang Hsu

Hsien-Hsin Sean Lee

Yu-Jung Chang

Yi-Kan Cheng

Nien-Yu Tsai

Min-Yuan Tsai

Ying-Yu Shen

Ken-Hsien Hsieh

Hsiao-Shu Chao

Hung Lung Lin

Li-Sheng Ke

HungLung Lin

Yuan-Te Hou

Gwan Sin Chang

Lee-Chung Lu

Huang-Yu Chen

Chung-Min Fu

Jian-Yi Li

Chien Lin Ho

Li-Chun Tien

Wen-Chun Huang

Jia-Rong Hsu

Hung-Lung Lin

C R Hsu

Chung-Yun Cheng

Ru-Gun Liu

Chung-Hsing Wang

Tsai-Sheng Gau

Yung-Sung Yen

Chien-Wen Chen

Ming-Hui Chih

Chin-Hsiung Hsu

Pi-Tsung Chen

Cheng-Chi Wu

Yung-Fong Lu

Rachid Salik

Wei-Long Wang

Fung Song Lee

Wen-Hao Chen

Kuo-Ji Chen

Jui-Feng Kuan

Ting Yu Chen

Tsong-Hua Ou

Yen-Hung Lin

Wei-Yi Hu

Zhe-Wei Jiang

Ching Fu Chang

Wen-Li Cheng

Yi-Chuin Tsai

Yu-Ren Chen

Chih Chi Hsiao

Yao-Jen Chuang

Jill Liu

Huan-Yung Chang

Godina Ho

I-Yun Leu

Jen-Kuei Wu

Yun-Yong Shen

Hsing-Lin Yang

Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.

Boundary cell

A system for manufacturing an integrated circuit includes a non-transitory computer readable medium configured to store executable instructions, and a processor coupled to the non-transitory computer readable medium. The processor is configured to execute the executable instructions for placing a set of gate layout patterns on a first layout level, and generating a cut feature layout pattern extending in the first direction. The set of gate layout patterns correspond to fabricating a set of gate structures of the integrated circuit. The cut feature layout pattern is on the first layout level, and overlap each of the layout patterns of the set of gate layout patterns at a same position in the second direction. The cut feature layout pattern identifies a location of a removed portion of a gate structure of the set of gate structures.

Integrated circuit and method of manufacturing the same

A semiconductor device includes a first cell. The first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. The semiconductor device further includes a second cell abutting the first cell. The second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.

Standard cell and semiconductor device including anchor nodes

An IC device includes an interlayer dielectric (ILD), a first tower structure embedded in the ILD, and a first ring region including a portion of the ILD that extends around the first tower structure. The first tower structure includes a plurality of first conductive patterns in a plurality of metal layers, and a plurality of first vias between the plurality of metal layers along a thickness direction of the IC device. The plurality of first conductive patterns and the plurality of first vias are coupled to each other to form the first tower structure. The plurality of first conductive patterns is confined by the first ring region, without extending beyond the first ring region. The first tower structure is a dummy tower structure.

Integrated circuit device and method

Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

Integrated circuit layout validation using machine learning

An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.

Standard cell and semiconductor device including anchor nodes and method of making

A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kgraph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.

Multi-patterning graph reduction and checking flow method

Integrated circuit and system of manufacturing the same

A method of manufacturing an integrated circuit includes generating a layout design of the integrated circuit, manufacturing the integrated circuit based on the layout design, and removing a portion of a gate structure of a set of gate structures thereby forming a first and a second gate structure. Generating the layout design includes placing a set of gate layout patterns and a cut feature layout pattern on the first layout level. The cut feature layout pattern extends in a first direction, overlaps the set of gate layout patterns and identifies a location of the portion of the gate structure of the set of gate structures. The set of gate layout patterns correspond to fabricating a set of gate structures. The set of gate layout patterns extending in a second direction and overlapping a set of gridlines that extend in the second direction.

Integrated circuit and method for manufacturing same

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Hsinchu, Taiwan

Wen-Ju Preet Yang