Macronix International Co., Ltd.

Wen Jer Tsai

Chih Chieh Yeh

Tao Cheng Lu

Yi Ying Liao

Chih Yuan Lu

Tien Fan Ou

Hsuan Ling Kao

Erh-Kun Lai

Yao Wen Chang

Han Chao Lai

Mam Tsung Wang

Tao-Cheng Lu

Chin Hsi Lin

Ful Long Ni

Der Shin Shyu

Shi Xian Chen

Ping Hung Tsai

Yi Yang Liao

Hung Yueh Chen

A non-volatile memory system includes a bit line and a plurality of memory cells associated with the bit line and coupled in a serial manner. The system further has a control circuitry in communication with the memory cells, wherein the control circuitry programs a target cell selected from the memory cells by applying a bit line voltage on the bit line in order to promote hot carrier injection into the target cell. The circuit also applies a programming voltage on the target cell under a hot carrier injection mechanism. Moreover, the circuit also applies a control voltage on a control cell, which is adjacent to the target cell when programming the target cell, wherein the control voltage is dependent on the threshold voltage of the control cell and the control voltage is less than the programming voltage.

Non-volatile memory capable of programming cells by hot carrier injection based on a threshold voltage of a control cell

A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.

Method for manufacturing a multiple-bit-per-cell memory

A multi-Level Cell (MLC) can be used to store, for example, 4 bits per cell by storing two bits on each of two sides. Each side can store, e.g., four different current level states that can be determined by the number of holes injected into, e.g., nitride layer, during programming. As more holes are injected the current decreases for a given voltage. The current can be low, therefore, it can be advantageous in one embodiment to use a current amplifier. The current amplifier can be a BJT, MOS or other type of device.

Systems and methods for programming a memory device

A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Gated diode nonvolatile memory process

In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the shallow trench isolation structures to different degrees. In some embodiments, a memory integrated circuit has memory circuitry with shallow trench isolation structures and intermediate regions. The memory circuitry supports a channel between neighboring nonvolatile memory devices supporting multiple current components with different orientations. In some embodiments, recessed shallow trench isolation structures are formed.

Recessed shallow trench isolation

A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal and a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Gated diode nonvolatile memory structure with diffusion barrier structure

A memory integrated circuit has memory arrays that are vertically layered. These memory arrays include word lines and bit lines. Intersections between the word lines and the bit lines include a diode and a memory state storage element. The diode and the memory storage element are connected in between a word line and a bit line. The diode at the intersections includes a first diode node and a second diode node. Various aspects of the memory integrated circuit are electrically interconnected in various ways, such as corresponding word lines, corresponding first diode nodes, or corresponding second diode nodes of different memory arrays being electrically interconnected. Various aspects of the memory integrated circuit are isolated in various ways, such as word lines, first diode nodes, or second diode nodes of different memory arrays being isolated.

Gated diode nonvolatile memory cell array

A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.

Integrated code and data flash memory

Gated diode nonvolatile memory operation

Charge trapping memory cells are protected from over-erasing in response to an erase command. For example, in response to an erase command, one bias arrangement is applied to program charge trapping memory cells, and another bias arrangement is applied to erase the charge trapping memory cells, such that the charge trapping memory cells have a higher net electron charge, in the erased state than i.n the programmed state. In another example, an integrated circuit with an array of charge trapping memory cells has logic which responds to an erase command by applying similar bias arrangements to the charge trapping memory cells. In a further example, such an integrated circuit is manufactured.

Method and apparatus for protection from over-erasing nonvolatile memory cells

A method of reducing gate disturb in a charge-trapping layer memory cell by applying different Vpass voltages to different sides of a selected wordline. A higher Vpass voltage is used to pass higher source/drain voltage and a lower Vpass voltage is used to pass a lower source/drain voltage. By controlling the Vpass voltages on different sides of a selected wordline, it is possible to reduce a vertical field that is established in a gate region when the Vpass voltages are applied. A reduced vertical field results in suppressed gate disturb. The method also includes a novel bit-line biasing scheme that may further reduce the vertical field and thereby may further suppress gate disturb, particularly in an array of memory cells.

Operation methods for a non-volatile memory cell in an array

A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Various embodiments may include or exclude a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Growing community of inventors

Hualien, Taiwan

Wen Jer Tsai