Taiwan Semiconductor Manufacturing Comp. Ltd.

Wen-I Hsu

Dun-Nian Yaung

Jen-Cheng Liu

Feng-Chi Hung

Min-Feng Kao

Jeng-Shyan Lin

Chun-Chieh Chuang

Tzu-Hsuan Hsu

Wen-De Wang

Shu-Ting Tsai

Shuang-Ji Tsai

Cheng-Ying Ho

Yeur-Luen Tu

Cheng-Hsien Chou

Jiech-Fun Lu

Chih-Yu Lai

Tsun-Kai Tsao

Ying-Ling Tsai

Kuo-Cheng Lee

Hsin-Chi Chen

Yen-Liang Lin

Hsun-Ying Huang

Keng-Yu Chou

Chien-Hsien Tseng

Chia-Yu Wei

Yu-Ting Kao

Chia-Shiung Tsai

Shih-Chang Liu

Yuichiro Yamashita

Chun-Hao Chou

Ching-Chun Wang

Chen-Jong Wang

Hsiao-Hui Tseng

Wei-Chieh Chiang

Yi-Shin Chu

Shih Pei Chou

Ching-Chung Su

Chun-Tsung Kuo

Ming-Hsien Yang

Feng-chi Hung

Jen-Shyan Lin

Kuan-Fu Lu

A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.

Stacked integrated circuits with redistribution lines

A semiconductor image sensing structure includes a substrate having a first region and a second region, a metal grid in the first region, and a hybrid metal shield in the second region. The hybrid metal shield includes a first metallization layer, a second metallization layer disposed over the first metallization layer, a third metallization layer disposed over the second metallization layer, and a fourth metallization layer disposed over the third metallization layer. An included angle of the second metallization layer is between approximately 40° and approximately 60°.

Semiconductor image-sensing structure and method for forming the same

A photodetector includes: a substrate; a first semiconductor region, the first semiconductor region extending into the substrate from a front side of the substrate; and a second semiconductor region, the second semiconductor region further extending into the substrate from a bottom boundary of the first semiconductor region, wherein when the photodetector operates under a Geiger mode, the second semiconductor region is fully depleted to absorb a radiation source received from a back side of the substrate.

Single photon avalanche diode

A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and an end cap dielectric layer is between the gate dielectric and the gate electrode over the implant isolation region.

Implant isolated devices and method for forming the same

An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.

Structure and method for 3D image sensor

An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded by a logic isolation feature. A radiation-sensing region is disposed in the pixel region of the substrate. An epitaxial pixel isolation feature is disposed in the pixel region and surrounds the radiation-sensing region. A doped region with a same doping polarity as the radiation-sensing region is located between a bottom of the radiation-sensing region and the back surface of the substrate. The epitaxial pixel isolation feature is in direct contact with the doped region. The doped region extends continuously under the pixel region and the logic region. The epitaxial pixel isolation feature is in direct contact with the doped region, and the logic isolation feature is spaced apart from the doped region.

Mechanisms for forming image-sensor device with epitaxial isolation feature

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate having a first photodetector region and forming a gate material over the gate dielectric layer. A dielectric protection layer is deposited over the gate dielectric layer and a first sidewall spacer is formed along a side of the gate material. The dielectric protection layer extends from a first location directly over the first photodetector region to a second location between the first sidewall spacer and the gate dielectric layer.

Photodiode gate dielectric protection layer

A photodetector includes: a substrate having a first doping type; a first semiconductor region having a second doping type, the first semiconductor region extending into the substrate from a front side of the substrate; and a second semiconductor region having the first doping type, the second semiconductor region further extending into the substrate from a bottom boundary of the first semiconductor region, wherein when the photodetector operates under a Geiger mode, the second semiconductor region is fully depleted to absorb a radiation source received from a back side of the substrate.

Structure and method for 3D Image sensor

Mechanisms for forming image-sensor device with expitaxial isolation feature

In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate, and selectively forming a gate material over the gate dielectric layer. A gate dielectric protection layer is formed over the gate dielectric layer, and a first sidewall spacer is formed over the gate dielectric protection layer and flanking a side of the gate material. The gate dielectric protection layer continuously extends from between the first sidewall spacer and the gate dielectric layer to outside of the first sidewall spacer.

A system and method for isolating semiconductor devices is provided. An embodiment comprises an isolation region that is laterally removed from source/drain regions of semiconductor devices and has a dielectric material extending over the isolation implant between the source/drain regions. The isolation region may be formed by forming an opening through a layer over the substrate, depositing a dielectric material along the sidewalls of the opening, implanting ions into the substrate after the deposition, and filling the opening with another dielectric material.

Isolation for semiconductor devices

Growing community of inventors

Tainan, Taiwan

Wen-I Hsu