Texas Instruments Corporation

Wen-Hwa M Chu

Lily Springer

Sameer P Pendharkar

Shaibal Barua

James Garrett Homack

Haim Horovitz

Robert Graham Shaw

Paul C Mannas

A method of verifying consistency between a circuit schematic and a corresponding integrated circuit layout is disclosed. The method includes identifying a voltage condition associated with a portion of the circuit schematic, and assigning a pseudo diode to the portion of the circuit schematic that is uniquely associated with the identified voltage condition. The method further includes coding a pseudo layer associated with an integrated circuit layout of the circuit schematic in accordance with content of the assigned pseudo diode, and verifying consistency between the circuit schematic and the corresponding integrated circuit layout by extracting the pseudo layer from the integrated circuit layout and comparing information of the pseudo layer to the assigned pseudo diode in the circuit schematic.

Verification method with the implementation of well voltage pseudo diodes

Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage dependent design rule is applied to an edge of an area of the layout if the edge is not covered by a pseudo layer. A second voltage dependent design rule is, on the other hand, applied to the edge of the area if the edge is covered by the pseudo layer.

Edge recognition based high voltage pseudo layer verification methodology for mix signal design layout

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Plano, TX, United States of America

Wen-Hwa M Chu