Novatek Microelectronics Corp.

Wen-Hsuan Lin

Chung-Wen Wu

Wen-Chi Lin

Chun-Liang Chen

Chien-Cheng Tu

Sih-Ting Wang

Min-Jung Chen

Kuo-Chi Chen

An image processing unit including an always on circuit block and a non-always on circuit block is provided. When operating under a first operation mode, the non-always on circuit block receives a bias voltage from a power supply unit, so as to perform an image processing operation on an image input signal. When operating under a second operation mode, the non-always on circuit block stops receiving the bias voltage from the power supply unit, so as to stop the image processing operation, and at least a microcontroller of the non-always on circuit block is powered down. One of the always on circuit block and the non-always on circuit block controls the power supply unit to stop supplying the bias voltage to the non-always on circuit block according an event trigger signal, such that the non-always on circuit block enters the second operation mode from the first operation mode.

Image processing unit, image processing apparatus and image display system

In a normal mode, the power supply is fed back in a close loop, but in a power saving mode, the power supply is fed back in an open loop. When it is detected that the power supply is continuously fed back in the open loop and in a substantially zero output status, the power supply circuit enters a power down status. If the back-stage circuit needs power supply again, then the feedback is switched to the close loop and the power supply circuit enters the normal mode.

Power supply circuit and method thereof

An image processing method for a display device, for enhancing image quality, includes receiving video signals, sequentially generating a plurality of image data according to the video signals, and sequentially displaying the plurality of image data on a panel of the display device. Each of the plurality of image data includes a frame data and a low-gray-level frame data respectively corresponding to a frame output duration and a vertical blanking duration in a timing sequence of the video signals.

Image processing method and related apparatus for a display device

A method and an apparatus for interlace scanning video signal frequency multiplication are provided. The method includes the following steps: first, removing a part of a first vertical synchronous signal (V-sync signal) which is asynchronous with a first horizontal synchronous signal (H-sync signal); next, capturing a first field and a second field from an interlace scan video signal according to the first V-sync signal obtained in the previous step; performing a frequency multiplication on a frame made up by the first and second fields, and producing a second V-sync signal and a second H-sync signal; finally, compensating for the second V-sync signal on a border between two fields of the frame after the frequency multiplication according to the second H-sync signal. Thereby, the method can be used to perform frequency multiplication using a line buffer instead of a frame buffer, to output through interface scanning without sacrificing image quality.

Apparatus and method for interlace scanning video signal frequency multiplication

To reduce production cost, the present invention provides a microprocessor device for an LCD controller, which includes a memory, a first processing unit, a second processing unit, a first arbiter and a second arbiter. The memory is utilized for storing data. The first processing unit is utilized for executing a first program. The second processing unit is utilized for executing a second program. The first arbiter is coupled to the first processing unit and the second processing unit and utilized for deciding an operation order for the first processing unit and the second processing unit. The second arbiter is coupled to the first processing unit, the second processing unit and the memory and utilized for deciding a memory accessing order for the first processing unit and the second processing unit.

Microprocessor device and related method for a liquid crystal display controller

An automatic clamping analog-to-digital converter (A/D converter) is provided, which includes an A/D converter, a switch, a comparator, a bidirectional counter, and a digital-to-analog converter (D/A converter). Wherein, the A/D converter receives an analog signal from a node, and then converts the analog signal into a digital signal according to a DC offset level. The switch is coupled between the node and a fixed voltage level, and is turned on or off according to a clamping signal. The comparator outputs a compare signal according to a comparison result between the digital signal and an offset value. The bidirectional counter outputs a count, and increases or decreases the count according to the compare signal. The D/A converter converts the count into the DC offset level and provides the DC offset level to the A/D converter.

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Taipei County, Taiwan

Wen-Hsuan Lin