Taiwan Semiconductor Manufacturing Comp. Ltd.

Wen-Hsiung Lu

Ming-Da Cheng

Chung-Shi Liu

Chih-Wei Lin

Hsien-Wei Chen

Tsung-Yuan Yu

Mirng-Ji Lii

Hsuan-Ting Kuo

Wei-Hung Lin

Chen-En Yen

Hsu-Lun Liu

Hsiu-Jen Lin

Meng-Tse Chen

Kuei-Wei Huang

Yu-Peng Tsai

Chia-Wei Tu

Yi-Wen Wu

Lung-Kai Mao

Chun-Cheng Lin

Yung-Sheng Lin

Cheng-Jen Lin

Chin-Wei Kang

Cheng-Ting Chen

Chen-Hua Douglas Yu

Chen-Shien Chen

Po-Hao Tsai

Hung-Jen Lin

Wei-Yu Chen

Tsung-Fu Tsai

Hui-Min Huang

Chin-Yu Ku

Yian-Liang Kuo

Cheng-Lung Yang

Chin Wei Kang

Kai-Jun Zhan

Su-Fei Lin

Tsung-Ding Wang

Ming-Che Ho

Chien-Hsiun Lee

Bor-Ping Jang

Chang-Jung Hsueh

Ting-Li Yang

Yung-Han Chuang

Jhao-Yi Wang

Kuanchih Huang

Tsung-Shu Lin

Meng-Wei Chou

Chang-Chia Huang

Kai-Di Wu

Chien-Pin Chan

Bor-Rung Su

Fu Wei Liu

Chien Ling Hwang

Sheng-Yu Wu

Cheng-Chung Lin

Ying-Jui Huang

Song-Bor Lee

De-Yuan Lu

Tzy-Kuang Lee

Zheng-Yi Lim

Cheng Jen Lin

Kuo Cheng Lin

Wen-Che Chang

Jacky Chang

Neng-Chieh Chang

Hao-Yi Tsai

Hung-Jui Kuo

Yu-Feng Chen

Yu-Chih Huang

Kuo-Ching Hsu

Hong-Seng Shue

Ai-Tee Ang

Ching-Wen Chen

Tsai-Tsung Tsai

Chao-Yi Wang

Tzong-Hann Yang

Ming-Hong Cha

Chia-Tung Chang

Kuan-Liang Lai

Chien-Chun Wang

Tzong-Huann Yang

Tang-Wei Huang

Fu-Wei Liu

Chia-Li Lin

Chih-Hsiang Tseng

A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.

Redistribution lines having nano columns and method forming same

A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

Redistribution lines with protection layers and method forming same

In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

Bump structure and method of making the same

In an embodiment, a device includes: a dielectric layer over an active surface of a semiconductor substrate; a conductive via in the dielectric layer, the conductive via including a first copper layer having a non-uniform grain orientation; and a bonding pad over the conductive via and in the dielectric layer, the bonding pad including a second copper layer having a uniform grain orientation, a top surface of the bonding pad being coplanar with a top surface of the dielectric layer.

Die bonding pads and methods of forming the same

Some devices included a substrate; and a through via, including a plurality of scallops adjacent the through via in a first region and a plurality of scallops adjacent the through via in a second region, the plurality of scallops having a first depth, the scallops having a greater depth. Some devices include an opening extending into a substrate, including a first region and a second region. Sidewalls of the opening include a stack of first concave portions extending a first distance into the first substrate, and a stack of second concave portions extending a second distance, greater than and parallel to the first distance, into the first substrate. A conductor partially fills the first concave portions and at least partially fills the respective second concave portions.

Semiconductor device and method

A semiconductor device includes a substrate, at least one via, a liner layer and a conductive layer. The substrate includes an electronic circuitry. The at least one via passes through the substrate. The at least one via includes a plurality of concave portions on a sidewall thereof. The liner layer fills in the plurality of concave portions of the at least one via. The conductive layer is disposed on the sidewall of the at least one via, covers the liner layer, and extends onto a surface of the substrate. The thickness of the conductive layer on the sidewall of the at least one via is varied.

Method of forming semiconductor device having at least one via including concave portions on sidewall

A semiconductor package structure includes a conductive pad formed over a substrate. The semiconductor package structure also includes a passivation layer formed over the conductive pad. The semiconductor package structure further includes a first via structure formed through the passivation layer and in contact with the conductive pad. The semiconductor package structure also includes a first encapsulating material surrounding the first via structure. The semiconductor package structure further includes a redistribution layer structure formed over the first via structure. The first via structure has a lateral extending portion embedded in the first encapsulating material near a top surface of the first via structure, and the lateral extending portion has a width increasing in a direction toward the redistribution layer structure.

Semiconductor package structure comprising via structure and redistribution layer structure

A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.

Arched membrane structure for MEMS device

Some devices included a substrate; and a through via, including a plurality of scallops adjacent the through via in a first region and a plurality of scallops adjacent the through via in a second region, the of scallops having a first depth, the scallops having a greater depth. Some devices include an opening extending into a substrate, including a first region and a second region. Sidewalls of the opening include a stack of first concave portions extending a first distance into the first substrate, and a stack of second concave portions extending a second distance, greater than and parallel to the first distance, into the first substrate. A conductor partially fills the first concave portions and at least partially fills the respective second concave portions.

A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

Package component with stepped passivation layer

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, active devices and transparent conductive patterns. The active devices are formed on the semiconductor substrate. The transparent conductive patterns are formed over the active devices and electrically connected to the active devices. The transparent conductive patterns are made of a metal oxide material. The metal oxide material has a first crystalline phase with a prefer growth plane rich in oxygen vacancy, and has a second crystalline phase with a prefer growth plane poor in oxygen vacancy.

Semiconductor device and manufacturing method thereof

Semiconductor device having at least one via including concave portions on sidewall

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Jhonghe, Taiwan

Wen-Hsiung Lu