Taiwan Semiconductor Manufacturing Comp. Ltd.

Wen-Hsien Tu

Wei-Fan Lee

Chee-Wee Liu

Fang-Liang Lu

Dong-Jie Ke

Yee-Chia Yeo

Chih-Sheng Chang

Cheng-Yi Peng

Shih-Hsien Huang

CheeWee Liu

A method of manufacturing a semiconductor device includes forming a fin structure protruding from a first isolation insulating layer disposed over a substrate, and forming a dummy gate structure over an upper portion of the fin structure. The method further includes forming a second isolation insulating layer over the first isolation insulating layer and forming gate sidewall spacers on opposing side faces of the dummy gate structure. The method also includes after the gate sidewall spacers are formed, forming a trench by etching a source/drain region of the fin structure and forming a base semiconductor epitaxial layer in the trench. The method further includes forming a cap semiconductor epitaxial layer on the base semiconductor epitaxial layer, removing the dummy gate structure to expose the fin structure, and forming a gate dielectric layer over a channel region of the fin structure.

Method of manufacturing a semiconductor device and a semiconductor device

The present disclosure is directed to semiconductor structures with source/drain epitaxial stacks having a low-melting point top layer and a high-melting point bottom layer. For example, a semiconductor structure includes a gate structure disposed on a fin and a recess formed in a portion of the fin not covered by the gate structure. Further, the semiconductor structure includes a source/drain epitaxial stack disposed in the recess, where the source/drain epitaxial stack has bottom layer and a top layer with a higher activated dopant concentration than the bottom layer.

Source and drain epitaxial layers

An integrated circuit device is provided. The integrated circuit device includes a semiconductor substrate, first and second semiconductor fins over the semiconductor substrate, and first and second epitaxy structures respectively on the first and second semiconductor fins. The first epitaxy structure is merged with the second epitaxy structure, and a bottom surface of the second epitaxy structure is lower than a bottom surface of the first epitaxy structure.

Integrated circuit device

The present disclosure is directed to source/drain (S/D) epitaxial structures with enlarged top surfaces. In some embodiments, the S/D epitaxial structures include a first crystalline epitaxial layer comprising facets; a non-crystalline epitaxial layer on the first crystalline layer; and a second crystalline epitaxial layer on the non-crystalline epitaxial layer, where the second crystalline epitaxial layer is substantially facet-free.

Semiconductor structure having a source/drain epitaxial stack with a non-crystalline layer therein

A semiconductor device includes a fin structure protruding from a first isolation insulating layer provided over a substrate, a gate dielectric layer disposed over a channel region of the fin structure, a gate electrode layer disposed over the gate dielectric layer, a base semiconductor epitaxial layer disposed over a source/drain region of the fin structure, and a cap semiconductor epitaxial layer disposed over the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a different lattice constant than the base semiconductor epitaxial layer, and a surface roughness of the cap semiconductor epitaxial layer along a source-to-drain direction is greater than zero and smaller than a surface roughness of the base semiconductor epitaxial layer along the source-to-drain direction.

A method for manufacturing an integrated circuit device is provided. The method includes forming first, second, and third semiconductor fins over a semiconductor substrate, in which the second semiconductor fin is between the first and third semiconductor fins; forming first and second fin sidewall spacers respectively on a sidewall of a first portion of the first semiconductor fin and a sidewall of a first portion of the second semiconductor fin, wherein the first and second fin sidewall spacers are between the first and second semiconductor fins; recessing the first portions of the first and second semiconductor fins and a first portion of the third semiconductor fin; and forming first to third epitaxial features respectively on the recessed portions of the first to third semiconductor fins, wherein the second epitaxial feature is spaced apart from the first epitaxial feature and merged with the third epitaxial feature.

Integrated circuit device with epitaxial features having adjusted profile and method for manufacturing the same

Method of manufacturing a facet-free source/drain epitaxial structure having an amorphous or polycrystalline layer

A semiconductor device and a method of forming the same are disclosed. The device comprises a semiconductor substrate comprised of a first semiconductor material and having a plurality of isolation features, thereby defining a first active region and a second active region; a first fin semiconductor feature comprised of a second semiconductor material and formed in the first active region; and a second fin semiconductor feature comprised of a second semiconductor material and formed in the second active region. The first fin semiconductor feature is tensile strained and the second fin semiconductor feature is compressively strained.

Growing community of inventors

Hsinchu, Taiwan

Wen-Hsien Tu