Realtek Semiconductor Inc.

Tpo Displays Corporation

Toppoly Optoelectronics Corporation

Wen-Hsia Kung

Tzuo-Bo Lin

Wen-Che Wu

Chih-Yuan Yang

Ming-Dou Ker

Ya-Hsiang Tai

Yu-Pin Chou

Hong-Ta Liu

Ying-Hsin Lin

Bo-Yun Lin

Chun-Chieh Chan

Cheng-Hung Wu

Hsien-Chun Chang

Szu-Ping Chen

Cheng-Hua Wu

Chia-Lung Hung

Yi-Teng Chen

Hsin-Hung Yi

Kuo-Yang Li

Chia-Fen Lin

A system on a chip (SoC) includes an on-screen display (OSD) circuit, a memory control circuit, and an audio processor. The OSD circuit is arranged to control OSD of a text message. The memory control circuit is coupled to a memory, and is arranged to read a text-to-speech (TTS) data corresponding to the text message from the memory. The audio processor is coupled to the memory control circuit, and includes a TTS circuit, wherein the TTS circuit is arranged to: receive the TTS data from the memory control circuit, and generate an audio output according to at least the TTS data.

System on a chip and display system

A video processor chip includes a memory circuit, a frame rate converter circuit, and an image compensation circuit. The memory circuit includes first to third storage spaces. The frame rate converter circuit sequentially writes multiple frame data in video data to the first to the third storage spaces respectively, and reads second data in the frame data from the memory circuit to perform a frame rate conversion when first data in the frame data is written to the memory circuit. The second data is a previous frame data of the first data. The image compensation circuit reads third data in the frame data from the memory circuit when the frame rate converter circuit reads the second data, and performs an image compensation according to a difference between the second data and the third data. The third data is a previous frame data of the second data.

Video processor chip and video processing method

A scaler includes an input interface, an output Vsync pulse generating circuit and a data buffer circuit. The input interface is arranged to receive an input Vsync pulse and input image data. The output Vsync pulse generating circuit is arranged to accordingly generate a first output Vsync pulse and a first output request in response to the input Vsync pulse. The data buffer circuit is arranged to buffer the input image data and, in response to the first output request, output a first output frame according to the input image data. The output Vsync pulse generating circuit further generates a second output Vsync pulse and a second output request according to the first output Vsync pulse and a first predetermined period and in response to the second output request, the data buffer circuit further outputs a second output frame according to the input image data.

Scaler, display device and associated data processing method

A display controller disposed in a display device that includes a flash memory and an integrated circuit is provided. The flash memory stores display device information of the display device. The integrated circuit includes a first and a second power conversion circuit and an accessing circuit. The first power conversion circuit converts an external power received from an external power adapter to a power in a first power domain. The second power conversion circuit converts a host power received from a host to the power of a second power domain and outputs the power to a flash memory such that the flash memory operates accordingly. The accessing circuit operates according to the power of the second power domain to access and transmit the display device information from the flash memory to the host when the first power conversion circuit is not in operation.

Integrated circuit and operation method of the same

This invention discloses a clock generation circuit and a clock generation method for generating a clock. The clock generation circuit includes a reference clock generation circuit, which is installed in a chip for independently generating a reference clock; a temperature sensor for sensing an ambient temperature to generate temperature information; a temperature compensation module, coupled to the temperature sensor, for generating a temperature compensation coefficient according to the temperature information; and a clock adjusting circuit, coupled to the clock generation circuit, for generating the clock according to the reference clock and the temperature compensation coefficient. The temperature compensation module generates the temperature compensation coefficient dynamically such that the frequency of the clock approaches a target frequency and does not substantially vary with the temperature.

Clock generation circuit and method thereof

A control chip for power saving is provided. The control chip is configured to operatively receive a first voltage and a first bias voltage. The control chip includes a microcontroller unit and a low power module. The low power module is coupled to the microcontroller unit. The microcontroller unit receives the first voltage to control the operation of at least one component under an operating mode and to stop receiving the first voltage under a power saving mode. The low power module operatively receives the first bias voltage. When the microcontroller unit switches from the operating mode to the power saving mode, the low power module operatively generates a first control signal to cause the microcontroller unit to stop receiving the first voltage. When the low power module detects a trigger signal, the power module operatively generates a second control signal to cause the microcontroller unit to continue receiving the first voltage.

Control chip and system using the same for power saving

An over-drive controller applied to a display panel and a method for over-drive control are provided. The over-drive controller includes an analyzing unit and an over-drive delta value determining unit. The analyzing unit is arranged for analyzing information of a current pixel in order to generate an over-drive information. The over-drive delta value determining unit is coupled to the analyzing unit, and is arranged for determining an over-drive delta value according to the over-drive information. Herein the over-drive information includes a position information or a field information of the current pixel.

Over-drive controller applied to a display panel and method for over-drive control therein

A control device for three dimensional display has an image processor and a timing signal generator. The image processor is used for receiving a first and a second input image signals to generate a first, a second, and a third output image signals. The first output image signal comprises part of the first input image signal. The second output image signal comprises part of the first input image signal and part of the second input image signal. The third output image signal comprises part of the second input image signal. The timing signal generator is used for generating a first lens control signal for configuring a first lens to be non-opaque when the second output image signal is displayed on a display device, and generating a second lens control signal for configuring a second lens to be non-opaque when the third output image signal is displayed on the display device.

Device and method for 3-D display control

A representative Device and Method for 3-D Display Control is disclosed. The method for controlling stereo image display is disclosed. That is, to receive an image input signal wherein the image input signal includes a first refresh rate; to convert a frame rate of the image input signal to generate an image output signal, wherein the image output signal includes a second refresh rate which is higher than the first refresh rate, and includes a first image signal, a first VBI (Vertical Blanking Interval), a second image signal, a second VBI, a third image signal and a third VBI; to output a control signal for a left eye shutter of shutter glasses during a duration between the first VBI and a part of the second image signal; and to output a control signal for a right eye shutter of the shutter glasses during a duration between a part of the third image signal and the third VBI.

A differential signal generating device includes a control circuit and a differential signal driver receiving a single-ended signal. The control circuit receives a source signal and generates a control signal corresponding to a first mode when the source signal conforms with a first pre-defined state, and corresponding to a second mode when the source signal conforms with a second pre-defined state. Variations of the source signal are related to signal content of the single-ended signal. The differential signal driver is coupled to the control unit for receiving the control signal therefrom. The differential signal driver outputs a differential signal output according to the single-ended signal when the control signal corresponds to the first mode. The differential signal driver outputs a non-differential signal output when the control signal corresponds to the second mode.

Differential signal generating device with low power consumption

The invention discloses a display control device and method thereof. The display control device and method thereof utilize the phase deviation and the frequency deviation between the output signal and the input signal caused during channel switching to provide converting time acceptable by a display device and to achieve the objective of balancing the data stream transmission.

Digital display control device and method thereof

A method for reducing output rate of video data for DisplayPort sink device is disclosed. By reducing the size of a blank area in a video frame, the invention reduces a pixel rate to become compatible with more types of back-end circuits having lower processing rates.

Apparatus and method for reducing output rate of video data

The invention discloses a sink device. The sink device comprises a buffering unit and a clock generating unit. The buffering unit receives a decoding data according to a symbol clock signal, reads the decoding data according to a pixel clock signal, and generates a water level value. The clock generating unit receives the symbol clock signal to generate the pixel clock signal and adjusts a rate of the pixel clock signal according to the water level value and/or a phase difference signal.

Video sink device

An interface transmission device and method are disclosed. The interface device, located in a first device, includes a transmission interface and a receiving circuit. The transmission interface receives an initialization signal and an interface signal. The receiving circuit receives the initialization signal through the transmission interface, and acquires a bit length of the interface signal according to the initialization signal. Thereby, the first device resolves the interface signal according to the bit length.

Growing community of inventors

Taoyuan County, Taiwan

Wen-Hsia Kung