Ememory Technology Inc.

Wen-Hao Ching

Shih-Chen Wang

Ching-Sung Yang

Hsin-Ming Chen

Tsung-Mu Lai

Yen-Hsin Lai

Wei-Ren Chen

Chun-Yuan Lo

Chih-Hsin Chen

Te-Hsun Hsu

Wei-Chen Chang

Hau-Yan Lu

Chen-Hao Po

Yung-Hsiang Chen

Shao-Chang Huang

Ming-Chou Ho

Wei-Ming Ku

Chun-Hung Lu

Chun-Chieh Chao

Wen-Chuan Chang

A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

High voltage switch device

A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.

Multi-time programming non-volatile memory

A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.

Memory array with one shared deep doped region

A non-volatile memory includes a first memory cell. The first memory cell includes five transistors and a first capacitor. The first transistor includes a first gate, a first terminal and a second terminal. The second transistor includes a second gate, a third terminal and a fourth terminal. The third transistor includes a third gate, a fifth terminal and a sixth terminal. The fourth transistor includes a fourth gate, a seventh terminal and an eighth terminal. The fifth transistor includes a fifth gate, a ninth terminal and a tenth terminal. The first capacitor is connected between the third gate and a control line. The third gate is a floating gate. The second terminal is connected with the third terminal. The fourth terminal is connected with the fifth terminal. The sixth terminal is connected with the seventh terminal. The eighth terminal is connected with the ninth terminal.

Non-volatile memory

A method for improving a program speed of a memory includes acquiring a program level of the memory, comparing the program level of the memory with a valid level and a target level for generating a comparison result, and entering a first loop and/or a second loop for setting a program voltage of the memory according to the comparison result.

Method for improving a program speed and an erase speed of a memory

A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.

Memory cell with high endurance for multiple program operations

A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.

Non-volatile memory for high rewrite cycles application

A memory array includes a first memory page and a second memory page. The first memory page includes a first word line, a first select gate line, a first control line, a first erase line, and a plurality of first memory cells each coupled to the first word line, the first select gate line, the first control line, and the first erase line, and for receiving a bit line signal and a source line signal. The second memory page includes a second control line, a second erase line, and a plurality of second memory cells each coupled to the first word line, the first select gate line, the second control line, and the second erase line, and for receiving a bit line signal and a source line signal.

Memory array with memory cells arranged in pages

A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cell regions. Each of the memory cell regions includes a plurality of memory cells, a programming voltage control generator and an erase voltage control generator. The memory cells receives a programming control voltage through a control end point for programming operation, and the memory cells receives an erase control voltage through an erase end point for erasing operation. The programming voltage control generator provides the programming control voltage to the memory cells, and the erase voltage control generator provides the erase control voltage to the memory cells.

Flash memory apparatus with voltage boost circuit

The present invention provides a method of fabricating an erasable programmable single-poly nonvolatile memory, comprising the steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covering a surface of the first area, wherein the second gate oxide layer extends to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covering the first and the second gate oxide layers; and defining a second type doped region in the DDD region and defining first type doped regions in the second type well region.

Method of fabricating erasable programmable single-poly nonvolatile memory

A non-volatile memory cell comprises a coupling device, a first and a second select transistor, and a first and a second floating gate transistor is disclosed. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to the first floating gate transistor and the second select transistor. Moreover, the first select transistor, the first floating gate transistor, and the second select transistor are formed in a second conductivity region. The second floating gate transistor is formed in a third conductivity region, wherein the first conductivity region, the second conductivity region, and the third conductivity region are formed in a fourth conductivity region. The first conductivity region, the second conductivity region, and the third conductivity region are wells, and the fourth conductivity region is a deep well. The third conductivity region surrounds the first conductivity region and the second conductivity region.

Growing community of inventors

Hsinchu County, Taiwan

Wen-Hao Ching