Taiwan Semiconductor Manufacturing Comp. Ltd.

Wen-Hao Chen

Yuan-Te Hou

Hung-Chih Ou

Chun-Yao Ku

Meng-Kai Hsu

Chin-Hsiung Hsu

Huang-Yu Chen

Chung-Hsing Wang

Shao-Huan Wang

Sheng-Hsiung Chen

Ming-Tao Yu

Chi-Yeh Yu

Jyun-Hao Chang

Lee-Chung Lu

Yi-Kan Cheng

Ru-Gun Liu

Chih-Ming Lai

Jiann-Tyng Tzeng

Chih-Liang Chen

Charles Chew-Yuen Young

Kam-Tou Sio

Chun-Kuang Chen

Chun-Chen Chen

Chung-Min Fu

Yen-Pin Chen

Pin-Dai Sue

Tsong-Hua Ou

King-Ho Tam

Fang-Yu Fan

Shih-Wei Peng

Stefan Rusu

Wun-Jie Lin

Kuo-Ji Chen

Yung-Sung Yen

Yu-Ti Su

David Barry Scott

Keh-Jeng Chang

Rabiul Islam

Po-Chia Lai

Meng-Fu You

Shu-Yi Ying

Hsiang-Ho Chang

Shen-Feng Chen

Kuo-Fu Lee

Prasenjit Ray

Kuan-Te Li

Chih-Yeh Yu

Li-Chun Tien

Dian-Hau Chen

Chih-Hsiang Yao

Cheng-I Huang

Chung-Kai Lin

Kuang-Hung Chang

Kuan-Ting Chen

Shao-huan Wang

Hui-Zhong Zhuang

Wen-Chun Huang

Yun-Han Lee

Wen-Ju Preet Yang

Chin-Chang Hsu

Ke-Ying Su

Chii-Ping Chen

Ting Yu Chen

Ming-Hsien Lin

Hsien-Hsin Sean Lee

Shyue-Shyh Lin

Wan-Yu Lo

Zhe-Wei Jiang

Ching Fu Chang

Ho Che Yu

Mark Shane Peng

Chia-Ming Ho

Kumar Lalgudi

Chung-Sheng Yuan

Yu-Hsiang Kao

Shu-Yu Chen

Hsien-Te Chen

Ming-Chyuan Chen

Pi-Cheng Chen

Ming-Huei Tsai

Adari Rama Bhadra Rao

Godina Ho

Dinesh Baviskar

An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Method and system for latch-up prevention

A device including first track groups on a first conductive layer of an integrated circuit. Each of the first track groups including at least one of a different first track group pitch, a different first track group spacing, and a different first track group width than the other first track groups. Where each of the first track groups includes first tracks that have at least one of a different first track width and a different first track spacing than the first tracks in the other first track groups.

Variable tracks and non-default rule routing

A multi-bit flip-flop includes a first flip-flop and a second flip-flop. The first flip-flop has a first driving capability. The first flip-flop includes a first set pin configured to receive a first set signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second set pin configured to receive the first set signal, and the first set pin and the second set pin are coupled together. The first flip-flop and the second flip-flop are configured to share at least a first clock pin.

Integrated circuit and method of forming same and a system

A semiconductor device includes a first circuit element, a layer of dielectric material, a first wire and a second wire in the layer of dielectric material, and an array of wires in the layer of dielectric material, wherein a first wire at a first track in the array of wires is electrically connected to the first circuit element, the first wire having a first width, a second wire at a second track in the array of wires has a second width different from the first width, and a third track in the array of wires between the first track and the second track is an empty track, and wherein the first wire is asymmetric with respect to the first track in the array of wires.

Semiconductor device for regulating integrated circuit timing and power consumption

A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.

Semiconductor process technology assessment

A discrete multi-row height cell in a hybrid row-height system with a plurality of rows of at least two different row-heights is disclosed. The discrete multi-row height cell includes: a first sub-cell deployed on a first row with a first row-height; a second sub-cell deployed on a second row with a second row-height, wherein the second row and the first row is separated by a third row with a third row-height, wherein the third row-height is different from the first row-height, wherein the first sub-cell and the second sub-cell are electrically connected by at least a wire.

Multi-row standard cell design method in hybrid row height system

A device including a first supply voltage track, a second supply voltage track, a first reference track, a first standard cell, and a second standard cell. The first supply voltage track is configured to provide a first voltage and the second supply voltage track is configured to provide a second voltage that is greater than the first voltage. The first standard cell is configured to be electrically connected to the first supply voltage track to receive the first voltage and electrically connected to the first reference track. The second standard cell is configured to be electrically connected to the second supply voltage track to receive the second voltage and electrically connected to the first reference track.

Multiple supply voltage tracks and standard cells

Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design. According to some embodiments, conducting placement and optimization further includes: moving the at least one spare cells to locations to abut the at least one timing critical cells to form pattern-S for each of the at least one timing critical cells.

System and method for improving design performance through placement of functional and spare cells by leveraging LDE effect

A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability, and includes a first reset pin configured to receive a first reset signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second reset pin configured to receive the first reset signal, and the first reset pin and the second reset pin are coupled together. The first inverter is configured to receive a first clock signal on a first clock pin, and configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.

A method includes: providing a first layout of a first layer over a substrate, the first layer having at least one metal pattern, and generating a second layout by placing a cut mask at a first position relative to the substrate to remove material from a first region of the at least one metal pattern to provide a first metal pattern and placing the cut mask at a second position relative to the first layer over the substrate to remove material from a second region of the at least one metal pattern to provide a second metal pattern.

Method of cutting conductive patterns

A method of forming an integrated circuit includes placing a first and a second standard cell layout design of the integrated circuit on a layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height. Placing the first standard cell layout design includes placing a first set of pin layout patterns on a first layout level over a first set of gridlines, extending in a first direction, and having a first width in a second direction. Placing the second standard cell layout design includes placing a second set of pin layout patterns on the first layout level over a second set of gridlines, extending in the first direction, and having a second width in the second direction.

Integrated circuit and method of forming the same

Method of regulating integrated circuit timing and power consumption

Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect(LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design. According to some embodiments, conducting placement and optimization further includes: moving the at least one spare cells to locations to abut the at least one timing critical cells to form pattern-S for each of the at least one timing critical cells.

Growing community of inventors

Hsin-Chu, Taiwan

Wen-Hao Chen