Synaptics Corporation

Synopsys, Inc.

Kilopass Technology, Inc.

Altima Communication, Inc.

Wen Fang

John Weinerth

Jorge Saucedo

Chinh Vo

Wen-Chung Wu

James Liu

A processing system comprises a sensing module, a first internal diagnostic mechanism, and a determination module. The sensing module is configured to couple with a first sensor electrode path of a plurality of sensor electrode paths, wherein the sensing module is configured to drive the first sensor electrode path with a first signal. The first internal diagnostic mechanism configured to couple with a second sensor electrode path and configured to acquire a test signal output while the sensing module drives the first sensor electrode path with the first signal. The first internal diagnostic mechanism comprises a selectable current source configured to couple with the second sensor electrode path, and wherein the selectable current source is enabled during acquisition of the test signal output. The determination module configured to determine whether the first and second sensor electrode paths are ohmically coupled together based on the test signal output.

Sensor electrode path error diagnosis

An output circuit at the output of an LDO regulator has two FETs (Field-Effect Transistors), a current source and a capacitor. The first FET is connected to the LDO output and a second voltage supply. The second FET is connected in series with the current source between the LDO output and the second voltage supply. The second FET is connected to the first FET in such a matter that a bias voltage is supplied to the first FET so that in static conditions the first FET draws predetermined amounts of current from the LDO output and to divert the predetermined amounts of current to the LDO output or to draw additional amounts of current from the LDO output to compensate for transient currents on the LDO output and to reduce variations in the output voltage of the LDO regulator. The capacitor with the current source defines a time constant to control the recovery of the output circuit from sudden drops or rises in voltage at the LDO regulator output to allow the LDO regulator to respond without adverse effect to the LDO output voltage.

Circuit for low-dropout regulator output

Bandgap Voltage Reference circuits configured to produce reference voltages with both voltage offset and a voltage temperature slope are disclosed. By generating the voltage offset from a temperature-independent current, the voltage offset of the reference voltage may be temperature-independent, while generating the voltage temperature slope from a temperature-dependent current allows the voltage temperature slope to vary with temperature. To ensure that the voltage offset remains independent from the voltage temperature slope, an apparatus is disclosed for orthogonal trimming of voltage offset and voltage temperature slope.

CMOS low voltage bandgap reference design with orthogonal output voltage trimming

A processing system for a capacitive sensing input device comprises a sensing module, a first internal diagnostic mechanism, and a determination module. The sensing module is configured to couple with a first sensor electrode path of a plurality of sensor electrode paths, and is configured to drive the first sensor electrode path with a first signal. The first internal diagnostic mechanism is configured to couple with a second sensor electrode path and to acquire a test signal output while the sensing module drives the first sensor electrode path with the first signal. The first internal diagnostic mechanism comprises a selectable current source configured to couple with the second sensor electrode path, and the selectable current source is enabled during acquisition of the test signal output. The determination module is configured to determine whether the first and second sensor electrode paths are ohmically coupled together based on the test signal output.

A processing system configured for capacitive sensing comprises transmitter circuitry, a first internal diagnostic mechanism, and a determination module. The transmitter circuitry is coupled with a first transmitter path of a plurality of transmitter paths and configured to transmit a first transmitter signal with the first transmitter path, wherein each transmitter path of the plurality of transmitter paths is configured for capacitive sensing. The first internal diagnostic mechanism is coupled to a second transmitter path of the plurality of transmitter paths. The first internal diagnostic mechanism is configured to acquire a first resulting signal while the transmitter circuitry transmits the first transmitter signal with the first transmitter path, wherein the first internal diagnostic mechanism comprises a selectable leakage path coupled to the transmitter circuitry. The determination module is further configured to determine that the first transmitter path is ohmically coupled to the second transmitter path of the plurality of transmitter paths based upon the first resulting signal.

Input device transmitter path error diagnosis

A processing system configured for capacitive sensing comprises transmitter circuitry, a first internal diagnostic mechanism, and a determination module. The transmitter circuitry is configured to transmit during a first time period with a first transmitter path of a plurality of transmitter paths in an input device. Each transmitter path of the plurality of transmitter paths is configured for capacitive sensing. The first internal diagnostic mechanism comprises a selectable leakage path. The selectable leakage path is configured to be coupled with the transmitter circuitry. The determination module is configured to determine if a discontinuity exists within the first transmitter path based on a discharge rate for the first transmitter path. The discharge rate is acquired during a second time period via the selectable leakage path of the first internal diagnostic mechanism, wherein the second time period occurs after the first time period.

Circuits for the restoration of a drooped signal are disclosed. In the asynchronous mode circuit, the drooped signal can be restored by detecting the peak of the positive amplitude and the peak of the negative amplitude and take the difference between the two peaks. This difference signal is fed back the equalizer. In the synchronous mode circuit, the drooped signal is sliced and passed to a regeneration circuit. The regeneration circuit uses reference voltage signals and phase information from the slicer to generate a regenerated signal. The regenerated signal is compared with the equalized signal to generate a difference signal, again fed back to the equalizer. The sliced signal is also fed to a clock recovery circuit which recovers the clock signal embedded in the received signal. The two circuits can be combined to provide an optimal circuit for the restoration of a drooped signal.

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San Jose, CA, United States of America

Wen Fang