Taiwan Semiconductor Manufacturing Comp. Ltd.

Wen-De Wang

Dun-Nian Yaung

Jen-Cheng Liu

Jeng-Shyan Lin

Chun-Chieh Chuang

Shuang-Ji Tsai

Min-Feng Kao

Tzu-Hsuan Hsu

Keng-Yu Chou

Cheng-Ying Ho

Pao-Tung Chen

Yueh-Chiou Lin

Feng-Chi Hung

Wen-I Hsu

Szu-Ying Chen

Shu-Ting Tsai

Hsiao-Hui Tseng

Kuo-Ming Wu

Yung-Lung Lin

Kuan-Liang Liu

Shou-Gwo Wuu

Hsin-Hui Lee

Jyh-Ming Hung

Alexander Kalnitsky

Chung-Yi Yu

Hsin-Hung Chen

Ching-Chung Su

Ching-Sheng Chu

Yu-Cheng Tsai

Meng-Hsien Lin

Guan-Hua Chen

Shine Chung

Shih Pei Chou

Ho-Ching Chien

Han-Chi Liu

Jhy-Ming Hung

Jen-Shyan Lin

Pao-Tung Cheng

Dun-Nian Yuang

A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate. The semiconductor device further includes a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate. The semiconductor device further includes a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, and a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip.

3DIC seal ring structure and methods of forming same

The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.

High capacitance MIM device with self aligned spacer

Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.

Back side illuminated image sensor with reduced sidewall-induced leakage

Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

Seal ring structures and methods of forming same

A semiconductor device structure includes a first chip, second chip, a first metal structure, a second metal structure, a first via structure and a second via structure. The first chip includes n inter metal dielectric (IMD) layer, which includes different materials adjacent to generate a number of staggered portions having a zigzag configuration. The second chip bonded to the first chip generates a bonding interface. The first metal structure is disposed in the first chip and between the staggered portions and the bonding interface. The first via structure in the first chip stops at the first metal structure. The first via structure includes a first via metal and a first via dielectric layer. A surface roughness of the staggered portions is substantially greater than a surface roughness of the first via dielectric layer. The second via structure extends from the first via structure to the second metal structure.

Semiconductor device structure and method for manufacturing the same

The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and an end cap dielectric layer is between the gate dielectric and the gate electrode over the implant isolation region.

Implant isolated devices and method for forming the same

A method includes bonding a Backside Illumination (BSI) image sensor chip to a device chip, forming a first via in the BSI image sensor chip to connect to a first integrated circuit device in the BSI image sensor chip, forming a second via penetrating through the BSI image sensor chip to connect to a second integrated circuit device in the device chip, and forming a metal pad to connect the first via to the second via.

Vertically integrated image sensor chips and methods for forming the same

An image sensor device includes a pixel array, a control circuit, an interconnect structure, and a conductive layer. The pixel array is disposed on a device substrate within a pixel region. The control circuit disposed on the device substrate within a circuit region, the control circuit being adjacent and electrically coupled to the pixel array. The interconnect structure overlies and electrically connects the control circuit and the pixel array. The interconnect structure includes interconnect metal layers separated from each other by inter-metal dielectric layers and vias that electrically connect between metal traces of the interconnect layers. The conductive layer disposed over the interconnect structure and electrically connected to the interconnect structure by an upper via disposed through an upper inter-metal dielectric layer therebetween. The conductive layer extends laterally within outermost edges of the interconnect structure and within the pixel region and the circuit region.

Image sensor device and method of forming same

An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed.

Pad structure exposed in an opening through multiple dielectric layers in BSI image sensor chips

Growing community of inventors

Minsyong, Taiwan

Wen-De Wang