Chunghwa Picture Tubes, Ltd.

National Yang Ming Chiao Tung University

Wen-Chuan Wang

Wei-Lien Sung

Shih-Chieh Lin

Han-Lung Liu

Shao-Lun Chang

Po-Tsun Liu

Bo-Han Chu

Guang-Ting Zheng

Chi-Liang Kuo

Yuan-Hao Chang

Wen-Che Wang

Yu-Fan Tu

Chang-Sheng Weng

Shao-Huan Hung

Shih-Chin Chen

A verification apparatus and a verification method are suitable for a touch display panel which comprises multiple partitions. The verification apparatus includes signal generating circuit and verification switch circuit. The signal generating circuit is configured to generate a verification voltage. The verification switch circuit comprises multiple switch units which are separately coupled to the partitions and the signal generating circuit, and are configured to deliver verification voltage simultaneously to at least two of multiple partitions.

Verification apparatus and verification method for touch display panel

A gate driving circuit is provided. The gate driving circuit includes multistage driving modules, where an Nstage driving module includes a setting circuit, a first driving circuit, an isolating switch circuit, a second driving circuit and an anti-noise circuit. The setting circuit generates a first precharge signal according to a gate driving signal of an (N&#x2212;2)scan line or a start signal. The isolating switch circuit coupled between the first driving circuit and the second driving circuit provides a second precharge signal, so as to effectively avoid a flickering problem of a display image caused by a surge of the gate driving signal due to a coupling effect of a parasitic capacitance of the transistor and a bootstrap capacitor, and meanwhile the bootstrap capacitor is not used, so as to effectively reduce a bezel area.

Gate driving circuit with isolating switch for display device using the same

A driving circuit in this disclosure includes plural stages of shift register circuits. Every stage in the shift register circuits includes an enabling control circuit, a first output circuit, a second output circuit and a disabling control circuit. The enabling circuit is configured to control the voltage of the first operation node according to enabling signal. The first output unit is configured to generate the first driving signal according to the voltage of the first operation node and the first clock signal. The second output unit is configured to generate the second driving signal according to the voltage of the first operation node and the second clock signal. The disabling control unit is used to pull low the voltage of the first operation node and output terminal of the first and second output unit to the reference voltage according to the first, third, and fourth clock signals.

Driving circuit and driving method

A display panel includes a substrate, and a pixel array and a gate driving circuit. The gate driving circuit provides gate driving signals to the pixel array, and includes shift registers, wherein each shift register includes a voltage providing unit, a first driving transistor, a voltage transmitting unit and a second driving transistor. The voltage providing unit receives a setting signal and a system high voltage to provide a first terminal voltage. The first driving transistor receives a first clock signal and the first terminal voltage to provide a first gate driving signal. The voltage transmitting unit receives the first gate driving signal to provide a second terminal voltage. The second driving transistor receives a second clock signal and the second terminal voltage to provide a second gate driving signal. Therefore, the influence caused by large difference of driving capabilities of the first and the second driving transistor is avoided.

Display panel

A capacitor structure of gate driver in panel (GIP) includes a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, a first and second transparent capacitor electrode layers. The first dielectric layer covers the first metal layer. The second metal layer is disposed on the first dielectric layer and coupled to the first metal layer. The second dielectric layer covers the second metal layer. The first transparent capacitor electrode layer is disposed on the first dielectric layer and connected to the second metal layer. The second transparent capacitor electrode layer is disposed on the second dielectric layer and coupled to the first metal layer, in which the second and first transparent capacitor electrode layers are arranged to be stacked in a thickness direction and mutually opposed across the second dielectric layer therebetween.

Capacitor structure of gate driver in panel

A fabrication method of an active device array substrate is disclosed. A first metal material layer, a gate insulation material layer, a channel material layer, a second metal material layer, and a first photoresist layer are formed over a substrate sequentially. The first photoresist layer is patterned with a multi-tone mask to form a first patterned photoresist layer with two thicknesses. A first and second removing processes are performed sequentially using the first patterned photoresist layer as a mask to form a gate, a gate insulation layer, a channel layer, and a source/drain. The first patterned photoresist layer is removed. A passivation layer and a second patterned photoresist layer are formed over the substrate. A third removing process is performed to form a plurality of contact holes. A pixel electrode material layer is formed over the substrate. The second patterned photoresist layer is lifted off to form a pixel electrode.

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Taipei, Taiwan

Wen-Chuan Wang