Taiwan Semiconductor Manufacturing Comp. Ltd.

Coretronic Corporation

Wen-Chih Yang

Harry Chuang

Chien-Liang Chen

Chii-Horng Li

Jin-Aun Ng

Chien-Hao Chen

Kuo-Tai Huang

Hao-Ming Lien

Jun-Lin Yeh

Kang-Cheng Lin

Chung-Hau Fei

Chi Hsin Chang

Chun Ming Lin

Mong-Song Liang

Bao-Ru Young

Mong Song Liang

Fan-Chieh Chang

Maxi Chang

Sheng-Yu Chiu

Ssu-Yi Li

Yung-Ta Chen

Ssu-Yu Li

Chien-Hau Fei

Chii-Horng Lee

An illumination system for a projection apparatus includes a light source module, an integrating rod and an optical detecting module. The light source module is capable of emitting an illuminating light beam. The integrating rod has a light entrance surface facing toward the light source module. The optical detecting module includes a light guiding device and an optical detecting device. The light guiding device has a first end surface and a second end surface. The first end surface is farther away from the light entrance surface of the integrating rod than the second end surface. The optical detecting device is disposed adjacent to the first end surface of the light guiding device and electrically connected to the light source module. The light source module is capable of adjusting intensity of the illuminating light beam according to randomly emitted light detected by the optical detecting device.

Illumination system

An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.

Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors

The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Method of fabricating a sealing structure for high-k metal gate

Sealing structure for high-K metal gate

The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.

Method for making a semiconductor device having metal gate stacks

An apparatus, and method of manufacture thereof, comprising a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first gate electrode having a first metal layer forming a first trench and a second metal layer filling the first trench, wherein the first and second metal layers have substantially different metallic compositions. The second semiconductor device includes a second gate electrode having a third metal layer forming a second trench and a fourth metal layer filling the second trench, wherein the third and fourth metal layers have substantially different metallic compositions, and wherein the first and third metal layers have substantially different metallic compositions.

Semiconductor device with high-K/dual metal gate

A semiconductor device using a CESL (contact etch stop layer) to induce strain in, for example, a CMOS transistor channel, and a method for fabricating such a device. A stress-producing CESL, tensile in an n-channel device and compressive in a p-channel device, is formed over the device gate structure as a discontinuous layer. This may be done, for example, by depositing an appropriate CESL, then forming an ILD layer, and simultaneously reducing the ILD layer and the CESL to a desired level. The discontinuity preferably exposes the gate electrode, or the metal contact region formed on it, if present. The upper boundary of the CESL may be further reduced, however, to position it below the upper boundary of the gate electrode.

Semiconductor device with discontinuous CESL structure

Growing community of inventors

Hsin-Chu, Taiwan

Wen-Chih Yang