Nan Ya Technology Corporation

Micron Technology Incorporated

Chung-hsin Electric & Machinery Mfg. Corporation

Inotera Memories, Inc.

Wen-Chieh Wang

Yi-Nan Chen

Hsien-Wen Liu

Tieh-Chiang Wu

Sheng-Wei Yang

Ting-Kuan Li

Chun-Der Chang

Sung-Feng Tsai

Su-Ying Lu

Yen-Haw Chen

Tse-Yao Huang

Hai-Han Hung

Ya-Chih Wang

Chih-Huang Wu

Chien-An Yu

Chin-Piao Chang

Yi-Fong Lin

Wei-Hui Hsu

Jin-Tau Huang

Jr-Rung Chen

Yuan-Sung Chang

Cheng-Shan Lin

The present application provides a method of manufacturing a memory device. The method includes steps of providing a semiconductor substrate; disposing a first supporting layer over the semiconductor substrate; disposing a first molding layer over the first supporting layer; disposing a second supporting layer over the first molding layer; removing a portion of the second supporting layer to form a first opening; disposing a second molding layer over the second supporting layer and within the first opening; forming a trench extending through the first supporting layer, the first molding layer, the second supporting layer and the second molding layer; disposing a conductive layer conformal to the trench; and removing the first molding layer and the second molding layer.

Method of manufacturing memory device having double sided capacitor

A memory device with a dielectric layer or an air gap between contacts and a method of making the same are disclosed. The method comprises a series of steps including forming a plurality of conductive lines having trenches therebetween; forming a contact layer in the trench; and forming a dielectric layer interposed in the contact layer and configured to divide the contact layer into two contacts. The method also comprises removing the dielectric layer to form a space and forming a cap layer over the two contacts to form an air gap therein. The method further comprises forming a second air gap between the conductive line and the two contacts.

Microelectronic devices including two contacts

Method for fabricating a memory device having two contacts

A micro grid stabilization device coupled to a DC bus and an AC bus in parallel is provided. A DC power generation apparatus provides power to the DC bus. An AC power generation apparatus provides power to the AC bus. A converter is coupled between the DC bus and the AC bus to transform the voltage of the DC bus and provide the transformed voltage to the AC bus. When the voltage of the DC bus or the AC bus is unstable, the micro grid stabilization device provides power to at least one of the DC bus and the AC bus to stabilize the power of the DC bus and the AC bus.

Micro grid stabilization device

A system and a control method of a mobile micro-grid are provided. The mobile micro-grid system includes a renewable energy source and a non-renewable energy source which are in a container. The control method includes supplying the renewable energy source as a primary power supply to an external load; and determining whether the electricity of the renewable energy source is sufficient. If the electricity of the renewable energy source is sufficient, then the renewable energy source provides electricity to the external load; if the electricity of the renewable energy source is not sufficient, then the renewable energy source and non-renewable energy source provide electricity to the external load. If an external power source, which is a renewable-energy-type power source, is connected to the mobile micro-grid system, then the renewable energy source and external power source work as the primary power supply.

Mobile micro-grid system and control method thereof

A method for forming a cell contact. A substrate having first and second protruding structures is prepared. An etch stop layer is deposited over the substrate. A sacrificial layer is deposited on the etch stop layer. The sacrificial layer is recessed. Spacers are formed on the top surface of the sacrificial layer. A portion of the sacrificial layer not covered by the spacers is etched away, thereby forming a recess. A gap filling material layer is deposited into the recess. An upper portion of the gap filling material layer and the spacers are removed to expose the top surface of the sacrificial layer. The sacrificial layer is removed to form contact holes. A punch etching process is performed to remove the etch stop layer from bottoms of the contact holes. The contact holes is filled up with a conductive material layer.

Method for forming cell contact

Provided is a method for fabricating a semiconductor device, which includes the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar, and a doped region is disposed at a bottom of each pillar. An insulation layer is formed below each doped region. In addition, a gate and a gate dielectric are formed on the sidewalls of each pillar.

Method for fabricating semiconductor device

A process of forming a slit in a substrate is provided. A mask layer is formed on a substrate, wherein the mask layer does not include carbon. An etching process is performed to be substrate by using the mask layer as a mask, so as to form a slit in the substrate. The etching gas includes Cl, CFand CHF, a molar ratio of CFto CHFis about 0.5-0.8, and a molar ratio of F to Cl is about 0.4-0.8, for example. Further, the step of performing the etching process simultaneously removes the mask layer.

Process of forming slit in substrate

A hard mask spacer structure includes a first spacer on a device layer, the first spacer defining a plurality of hole patterns and at least an asteriated hole pattern between the hole patterns; and a second spacer on the first spacer and inlaid into the asteriated hole pattern, thereby rounding the asteriated hole pattern.

Hard mask spacer structure and fabrication method thereof

A semiconductor process is provided. A mask layer is formed on a substrate and has a first opening exposing a portion of the substrate. Using the mask layer as a mask, a dry etching process is performed on the substrate to form a second opening therein. The second opening has a bottom portion and a side wall extending upwards and outwards from the bottom portion, wherein the bottom portion is exposed by the first opening and the side wall is covered by the mask layer. Using the mask layer as a mask, a vertical ion implantation process is performed on the bottom portion. A conversion process is performed, so as to form converting layers on the side wall and the bottom portion of the second opening, wherein a thickness of the converting layer on the side wall is larger than a thickness of the converting layer on the bottom portion.

Semiconductor process

A semiconductor process is provided. A substrate is provided in an etching apparatus, wherein first conductive patterns, a barrier layer and a patterned insulating layer are formed thereon. The first openings are formed between the first conductive patterns, the barrier layer covers surfaces of the first conductive patterns and the first openings, and the patterned insulating layer is formed on the first conductive patterns and has a plurality of second openings. The second openings expose the barrier layer on top corners of the first conductive patterns. Polymer layers are formed on the barrier layer, wherein a thickness of the polymer layer on the top corners of the first conductive pattern is larger than a thickness of the polymer layer on bottom portions of the first openings. An etching process is performed to remove the polymer layer and the barrier layer disposed on the bottom portions of the first openings.

A method of forming a shadow layer on a wafer bevel region is provided. First, a substrate having the wafer bevel region and a central region is provided. Thereafter, an upper insulator and a lower insulator are provided. The upper insulator is disposed on an upper surface of the substrate and at least covers the central region. The lower insulator is disposed on a lower surface of the substrate and at least covers the central region. A shadow layer is then formed on the upper surface which is not covered by the upper insulator and on the lower surface which is not covered by the lower insulator. Next, the upper insulator and the lower insulator are removed.

Growing community of inventors

Taoyuan, Taiwan

Wen-Chieh Wang