Mediatek Corporation

United Microelectronics Corp.

Arcady an Technology Corporation

Wen-Chieh Wang

Yu-Hsin Lin

Fong-Wen Lee

Khurram Muhammad

Chih-Ming Hung

Hsiang-Hui Chang

Chi-Hsueh Wang

Jy-Hwang Lin

Kuo-Shu Huang

Wei-Yang Teng

Tien-Shang Kuo

Ting-Yang Wang

Hua-Wei Peng

Yueh-Min Chen

I-Wen Liu

Chuan-Sheng Liu

Bo-Cheng Chen

Wei-Ru Tseng

Fu-Hsuan Chu

An amplification circuit with a common-mode voltage compensation circuit is shown. The common-mode voltage compensation circuit has a first compensation resistor coupled between an input terminal of a loop filter of the amplification circuit and a control node, and a second compensation resistor coupled between another input terminal of the loop filter and the control node. The control node is coupled to a power ground voltage when the two output signals of the amplification circuit are high, and it is coupled to a power supply voltage when the two output signals of the amplification circuit are low.

Amplification circuit with compensation for common-mode voltage fluctuation

A fast-transient buffer is shown. The fast-transient buffer has a flipped voltage follower coupled between the input terminal and the output terminal of the fast-transient buffer, and a first MOS transistor coupled to the flipped voltage follower as well as the output terminal of the fast-transient buffer. The first MOS transistor regulates the output voltage of the output terminal of the fast-transient buffer, in the opposite direction in comparison with an output voltage regulation direction due to the flipped voltage follower.

Fast-transient buffer

The present invention provides a quadrature phase detector including a detection circuit. The detection circuit includes a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.

Low power quadrature phase detector

The present invention provides a filtering circuit comprising a poly phase filter and a quadrature phase detector. The poly phase filter comprises a first path, a second path, a third path and a fourth path. The first path is configured to receive a first input signal to generate a first clock signal. The second path comprising a first adjustable delay circuit is configured to receive the first input signal to generate a second clock signal. The third path comprising a second adjustable delay circuit is configured to receive a second input signal to generate a third clock signal. The fourth path is configured to receive the second input signal to generate a fourth clock signal. The quadrature phase detector is configured to detect phases of these clock signals to generate control signals to control the first adjustable delay circuit and the second adjustable delay circuit.

Poly phase filter with phase error enhance technique

A class-D amplifier with good signal-to-noise ratio (SNR) performance is shown. The class-D amplifier includes a loop filter, a pulse-width modulation signal generator, a gate driver, a power driver, and a feedback circuit, which are configured to establish a closed amplification loop. The feedback circuit is configured to establish a feedback path. The class-D amplifier further includes a feedback breaker. The feedback breaker breaks the feedback path in response to conditions in which there no-signal information in the class-D amplifier.

Class-D amplifier with high dynamic range

A network path selection method and a network node device using the same are disclosed. The network path selection method includes: determining whether a first uplink time parameter table is received from the first relay node device and whether a second uplink time parameter table is received from the second relay node device; when the first uplink time parameter table is received from the first relay node device and the second uplink time parameter table is received from the second relay node device, calculating a first estimated uplink time parameter according to the first uplink time parameter table and a second estimated uplink time parameter according to the second uplink time parameter table; and determining to connect to a gateway via one of the first relay node device and the second relay node device according to the first estimated uplink time parameter and the second estimated uplink time parameter.

Network path selection method and network node device using the same

A semiconductor structure including a substrate, a light sensing device and a light-guiding structure is provided. The light sensing device is disposed in the substrate. The light-guiding structure is located above the light sensing device. The light-guiding structure has a top surface and a bottom surface opposite to each other, and the bottom surface is closer to the substrate than the top surface. A position of a minimum width of the light-guiding structure is located between the top surface and the bottom surface.

Semiconductor structure and manufacturing method thereof

A class-D amplifier includes a loop filter, a pulse-width modulation (PWM) circuit, an output circuit, and a common-mode control circuit. The loop filter receives an input signal of the class-D amplifier to generate a filtered signal. The PWM circuit converts a non-PWM signal into a PWM signal, wherein the non-PWM signal is derived from at least the filtered signal. The output circuit generates an output signal of the class-D amplifier according to the PWM signal. The common-mode control circuit monitors a common-mode level of the output signal to generate a common-mode control signal for PWM common-mode control.

Class-D amplifier with pulse-width modulation common-mode control and associated method for performing class-D amplification

A semiconductor structure includes a substrate, a plurality of image sensing devices formed in the substrate, at least a passivation layer formed on the substrate, a plurality of first metal patterns formed on the passivation layer, a plurality of gaps formed between the first metal patterns, an insulating layer lining the gaps, and a plurality of light-guiding structures respectively formed in the gaps. The light-guiding structures respectively include an anchor portion and a body portion, and bottom surfaces of the anchor portions being lower than top surfaces of the first metal patterns.

Semiconductor structure

A digital transmitter includes: a plurality of adjustable delay lines arranged to delay a plurality of digital input signals by a plurality of delay times to generate a plurality of delayed digital input signals respectively; a plurality of converting devices arranged to convert the plurality of delayed digital input signals into a plurality of converting signals respectively; and a calibration device arranged to adjust a delay time of at least one adjustable delay line in the plurality of adjustable delay lines to make the plurality of converting devices convert the plurality of delayed digital input signals at respective desire time points.

Digital transmitter and method for calibrating digital transmitter

A contact layout structure includes a substrate having at least a first region defined thereon, plural sets of first contact layouts positioned along a predetermined direction in the first region, and a plurality of second contact layouts positioned in the first region. Each set of the first contact layouts further comprises two square contact units and two adjacent rectangle contact units positioned in between the two square contact units. Each of the rectangle contact units comprises two opposite long sides and two opposite short sides, and a length of the long sides is not equal to the a length of the short sides.

Contact layout structure

A contact layout structure includes a substrate having at least a first region defined thereon, plural sets of first contact layouts positioned along a predetermined direction in the first region, and a plurality of second contact layouts positioned in the first region. Each set of the first contact layout has two square contact units and two adjacent rectangle contact units positioned between the two square contact units.

Growing community of inventors

Hsinchu, Taiwan

Wen-Chieh Wang