Macronix International Co., Ltd.

Megica Corporation

Memocom Corp.

Windbond Electronics Corp.

Waltop International Corporation

Wen-Chieh Lee

Mou-Shiung Lin

Jin-Yuan Lee

Chien-Kang Chou

Chiu-Ming Chou

Hong-Gee Fang

Yi-Cheng Liu

Wei-Chieh Wu

Ching-Wen Chen

Chang-Ting Chen

I-An Chen

Ching-Tang Wu

A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

Semiconductor chip with coil element over passivation layer

A serial advanced technology attachment (SATA) interface storage device. The SATA interface storage device can be used in cooperation with an electrical apparatus and comprises a substrate, a chip set, a SATA interface and a shell. The substrate has a first surface, a second surface corresponding to the first surface and a plurality of connectors between the first surface and the second surface. The chip set is disposed on the first surface. The SATA interface is disposed on the second surface and is electrically connected to the chip set via a part of the connectors so that the electrical apparatus may be electrically connected to the chip set via the SATA interface to access the chip set. The shell has a width and a thickness and defines a receiving space for receiving the substrate, the chip set and the SATA interface, where the width and the thickness conform to a micro-memory card standard.

Serial advanced technology attachment interface storage device

A method for operating a memory device that comprises periodically generating a refresh request signal for performing a refresh operation, providing an access request signal for performing an access operation, performing the refresh operation if the refresh request signal occurs prior to the access request signal, and performing the access operation if the access request signal occurs prior to the refresh request signal.

System and method for refreshing random access memory cells

A method of operating a dynamic random access memory (DRAM) using a bit line and a bit line bar is disclosed. The DRAM stores data by using a charge storage device, which is coupled to the bit line via a switch device. A voltage drop occurs when the switch device is turned on. The method programs the charge storage device with a first voltage or a zero voltage in response to a power voltage reduction due to the voltage drop. For accessing the data, the bit line and the bit line bar are charged to the power voltage, the switch device is turned on and the data stored in the charge storage device is determined according to a voltage difference between the bit line and the bit line bar.

Method of operating dynamic random access memory

A method of operating a memory device including an array of cells formed in rows and columns that comprises providing a control signal, activating the control signal, the activated control signal including a first state and a second state, continuously performing access cycles in response to the first state of the activated control signal in one part of a period, and continuously performing refresh cycles in response to the second state of the activated control signal in another part of the period.

Refresh methods for RAM cells featuring high speed access

A semiconductor memory with shielding effect is disclosed in the invention. The memory includes at least a plurality of word lines, one ground line control unit, and a plurality of memory units. Every memory unit includes a primary bit line, a ground line, a first equivalent switch, and a second equivalent switch. The primary bit line is enabled by a control signal. The ground line and the ground line control unit are electrically connected. The first equivalent switch is coupled to both the primary bit line and the ground line, and is controlled by the control signal of the previous memory unit. The second equivalent switch is coupled to both the primary bit line and the ground line of the next memory unit, and is controlled by the control signal of the next memory unit.

Memory with shielding effect

An integrated circuit with on-chip resources to support the testing of data stored on the integrated circuit includes logic to compute a check code using data, or a combination of data and addresses, of a particular data set stored on the device. The check code produced using the stored version of the data set is compared with a test code produced using a correct version of the data set, to indicate whether the correct data set was successfully stored on the device. An on-chip store holds the code produced using the correct version, and an on-chip comparator is used to produce a flag indicating the success or failure of the test. During manufacturing of the device, the memory tester simply tests the flag.

Integrated circuit with on-chip data checking resources

The present invention provides an apparatus for capturing images and for manipulating a cursor. The apparatus can be used for operation in a first mode and a second mode. The apparatus includes an opto-electronic mechanism that is provided for receiving image signals. The apparatus also has a user-selectable trigger that allows a user to assert or de-assert a mode signal that determines whether operation is desired in the first mode or the second mode. The apparatus has a controller that is coupled to the opto-electronic mechanism and user-selectable trigger for receiving the mode signal. When operation is in the first mode, the received image signals are processed and used to control movement of a cursor on a screen or display. When operation is in the second mode, the received image signals are processed and displayed as video images on a PC.

Optical mouse having an integrated camera

The present invention provides a ROM having a plurality of memory cell blocks each composed of a main bit line, a ground bit line, and a plurality of memory cells for storing information, which comprises: a plurality of up select transistors for selecting a memory cell block connected to the main bit line from a plurality of the memory cell blocks; and a plurality of down select transistors for selecting a memory cell block connected to the ground line from a plurality of the memory cell blocks, said up select transistors and down select transistors being arranged alternately with the memory cell block in between, wherein the layout pattern of said up select transistors and down select transistors being rotated 90 degrees. Under this kind of new layout pattern, the main bit lines and the ground bit lines will not be affected by the performing of ion implantation process, therefore, the junction leakage current will not be increased.

Growing community of inventors

Hsinchu, Taiwan

Wen-Chieh Lee