Shenzhen Goodix Technology Co., Ltd.

Vtc Electronics Corp.

Accton Technology Corporation

Wen-Chi Wang

Si Herng Ng

Julian Lin

Tai-Kuo Wang

Che-Yen Lee

Hsin-Min Wang

Ju-Chieh Liu

The present application discloses a PPG circuit, a biological characteristics detection device and a biological characteristics detection method. The PPG circuit is configured to control a light source and N photoelectric converters to sense biological characteristics of an object under test; the PPG circuit includes: a transmitting channel, K receiving channels, wherein the N photoelectric converters are divided into K sets of photoelectric converter sets, and the K receiving channels respectively correspond to K sets of photoelectric converter sets; and a controller, configured to control the PPG circuit to operate in a partial sampling phase or an full sampling phase, so as to generates J or K biological characteristics sampling results during each of the pulse repetition cycles.

Photoplethysmogram circuit, biological characteristics detection device and biological characteristics detection method

The present application discloses an amplifier circuit, a chip and an electronic device, which generates a positive output signal and a negative output signal according to a positive input signal and a negative input signal, wherein the positive input signal and the negative input signal have a corresponding input differential-mode voltage and input common-mode voltage, and the positive output signal and the negative output signal have a corresponding output differential-mode voltage and output common-mode voltage, and the amplifier circuit includes: an amplifying unit, configured to receive the positive input signal and the negative input signal and generate the positive output signal and the negative output signal; and an attenuation unit, including: a positive common-mode capacitor and a negative common-mode capacitor, configured to attenuate the input common-mode voltage below a first specific frequency.

Amplifier circuit, chip and electronic device

The present application discloses an asynchronous sampling architecture and a chip. The asynchronous sampling architecture is configured to receive a first input data string from the peer end, and the asynchronous sampling architecture includes: a first register, configured to buffer a first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end; and a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out as a first output data string from the first register according to the gated clock.

Asynchronous sampling architecture and chip

The present application discloses a transconductance amplifier and a related chip. The transconductance amplifier is configured to generate an output current according to a positive input voltage and a negative input voltage, wherein the transconductance amplifier includes: an input stage, configured to receive the positive input voltage and the negative input voltage and generate a positive output current and a negative output current, wherein the input stage includes: a first transistor, wherein a gate thereof is coupled to the positive input voltage; a second transistor, wherein a gate thereof is coupled to the negative input voltage; a first resistor, serially connected between the first transistor and the second transistor; a third transistor, wherein a source of the third transistor is coupled between the first resistor and the first transistor, and a drain of the third transistor is configured to output the positive output current; and a fourth transistor.

Transconductance amplifier and chip

The present application discloses a data converter (). The data converter includes an input terminus (), a digital-to-analog (D/A) converter () and a mapping unit (). The input terminus is configured to receive an input signal. The D/A converter includes a plurality of D/A converter units configured to generate an output signal. The mapping unit is coupled between the input terminus and the D/A converter and is configured to cause the plurality of D/A conversion units to be equivalently arranged in a relative order in which the plurality of D/A conversion units are gated according to specific electrical characteristics of the plurality of D/A conversion units for digital-to-analog conversion. The present application further provides an A/D converter, a D/A converter and a related chip.

Data converter and related analog-to-digital converter, digital-to-analog converter and chip

The present application discloses a voltage booster circuit and a related circuit, chip and wearable device. The voltage booster circuit has an output terminal, which provides an output voltage and a load current. The voltage booster circuit includes: a first charge pump, which provides a first bias current; a second charge pump, which provides the load current; an output voltage fixing circuit, which draws the first bias current from the first charge pump to the output terminal, wherein the output voltage fixing circuit fixes a first charge pump voltage of the first charge pump by fixing the first bias current and further fixes the output voltage based on the fixed first charge pump voltage; and a load current generation circuit, which draws the load current from the second charge pump to the output terminal based on a second charge pump voltage of the second charge pump.

Voltage booster circuit and related circuit, chip and wearable device

The present application discloses an ADC (). The ADC has an A/D conversion operation mode and a measurement operation mode. The ADC includes an input terminal (), a DAC (), and an output terminal (). The input terminal is configured to receive an analog signal. The output terminal is configured to output a digital signal. The DAC includes a plurality of D/A conversion units. When the ADC operates in the A/D conversion operation mode, the ADC is configured to convert the analog signal into the digital signal, and when the ADC operates in the measurement operation mode, the digital signal related to a ratio of a capacitance of the D/A conversion unit to be measured to a total capacitance of the plurality of D/A conversion units.

Analog-to-digital converter and associated chip

An operational amplifier includes: a first amplifier stage, configured to generate first output voltages according to first input voltages; a second amplifier stage, configured to generate second output voltages according to the first output voltages; a second output stage circuit, configured to replicate an equivalent or a scaled-down version of the first output stage circuit; a first common-mode feedback circuit, configured to keep an output common-mode voltage of the second output stage circuit at a predetermined value; a logic loop circuit configured to, when the operational amplifier operates in a direct current calibration phase, adjust a difference between the first output voltages; a bias circuit, configured to generate a voltage close to a common-mode voltage of the first output voltages produced after the operational amplifier is turned on, the voltage serving as a reference voltage of a second common-mode feedback circuit.

Operational amplifier and control method thereof

The application provides a charge pump circuit, includes a digital control circuit, coupled to the switch module, configured to receive a up digital signal and a down digital signal, and adjust a first output voltage to a voltage level of an input voltage and adjust an second output voltage to a ground voltage level according to the up digital signal and the down digital signal; a digital-to-analog converter (DAC), configured to generate a corresponding up reference voltage and a corresponding down reference voltage according to the up digital signal and the down digital signal; and a voltage follower, comprising a plurality of operational amplifiers and a plurality of transistor switches, configured to lock the first output voltage and the second output voltage according to the up reference voltage and the down reference voltage; wherein the up digital signal and the down digital signal are varied with time.

Charge pump circuit and controlling method thereof

The present application provides a vector quantization digital-to-analog conversion circuit, for converting a digital signal to an analog signal, characterized by includes a vector quantization circuit, configured to receive the digital signal and generate a vector quantization signal; a data weighted averaging circuit, coupled to the vector quantization circuit, including a plurality of data weighted averaging sub-circuits, configured to receive the vector quantization signal to generate a plurality of data weighted averaging signals; and a digital-to-analog conversion circuit, coupled to the data weighted averaging circuit, including a plurality of digital-to-analog conversion sub-circuits, configured to receive the data weighted averaging signal to generate the analog signal.

Vector quantization digital-to-analog conversion circuit for oversampling converter

The application provides a charge pump circuit, including a switch module, including a plurality of switches and a soft ramp-up switch, configured to generate a first output voltage and a second output voltage according to an input voltage; and a digital control circuit, coupled to the switch module, configured to receive a up digital signal and a down digital signal, and adjust the first output voltage to a voltage level of the input voltage and adjust the second output voltage to a ground voltage level according to the up digital signal and the down digital signal. The charge pump circuit of application has advantages of minimizing inrush currents to avoid circumstances of distortions caused by the pop noises or clipping and optimizing the efficiency of the amplifier.

The application provides a vector quantization digital-to-analog conversion circuit, applied to an oversampling converter, characterized that the vector quantization digital-to-analog conversion circuit includes a vector quantization circuit, configured to generate a vector quantization signal, a data weighted averaging circuit, coupled to the vector quantization circuit, including a plurality of data weighted averaging sub-circuits, configured to receive the vector quantization signal to generate a plurality of data weighted averaging signals; and a digital-to-analog conversion circuit, coupled to the data weighted averaging circuit, including a plurality of digital-to-analog conversion sub-circuits, configured to receive the data weighted averaging signal to generate the analog signal.

The present application provides a noise shaping circuit including a first modulation unit, configured to generate a first digital output signal according to a first digital input signal, the first modulation unit comprising a first quantizer; a first subtractor, coupled to an input terminal and an output terminal of the first quantizer, configured to generate a first quantization noise; and a second modulation unit, configured to generated a second digital output signal according to a second digital input signal, wherein the second digital input signal is related to the first quantization noise; wherein the noise shaping circuit generates an overall analog output signal according to the first digital output signal and the second digital output signal.

Noise shaping circuit and sigma-delta digital-to-analog converter

A transceiver includes an antenna, an impedance adjustment device, an RF (Radio Frequency) front-end circuit, a storage device, and a processor. The antenna receives an RF signal. The impedance adjustment device is coupled to the antenna, and includes a plurality of branch circuit with different impedance values and a switch module. The processor is coupled to the RF front-end circuit and controls the switch modules. In a comparison mode, the switch module selects to connect to the branch circuits individually, and the processor detects each RSSI (Received Signal Strength Indications) value corresponding to the branch circuit and records all of the RSSI values to the storage device respectively. In the comparison mode, the processor further compares the RSSI values to for highest one. Finally, the switch module selects the branch circuit corresponding to the highest RSSI value as a transmission branch.

Apparatus and method for impedance adjustment

The present invention relates to an intellectual surveillance system and a monitoring method thereof. The intellectual surveillance system comprises a camera module and a terminal computer module, wherein the camera module is capable of monitoring and reacting various sudden situations, and then the camera module transmits images and messages of the situations to the terminal computer module through at least one BNC connector and at least one coaxial cable, further that, the terminal module is able to display the images and show a alert so as to complete a secure monitor without any RS-485 series communication port and digital IP camera. Besides, the intellectual surveillance system can control the actions of monitoring and reacting such situations automatically by using the monitoring method.

Growing community of inventors

Guangdong, China

Wen-Chi Wang