Realtek Semiconductor Inc.

Wen-Chi Wang

Chao-Cheng Lee

Jui-Yuan Tsai

Yi-Shu Chang

Jui-Cheng Huang

Chang-Shun Liu

Yi-Chang Tu

Tze-Chien Wang

Chia-Liang Chiang

Shih-Yu Ku

Chu-Ting Su

Bing-I Chang

Chieh-Chuan Chin

Yung-Hao Lin

Fu-Yi Hsieh

Jul-Cheng Huang

A data weighted average circuit is disclosed which includes a lookup unit and a storage unit. The invention uses a lookup table to speed up the circuit operation. Besides, the operation delay is not affected by various orders of the data weighted average circuit and various bit-widths of input data.

Data weighted average circuit and dynamic element matching method

An apparatus and method of automatic identification an external audio input/output device. The external device connected to an audio jack is identified as an audio output or input device, according to the impedance thereof. Furthermore, the present invention automatically selects the most suitable internal circuit to connect to the external device.

Apparatus for automatic identification of audio input/output device and method thereof

A sigma-delta modulator and an output rate reduction method are disclosed. The sigma-delta modulator comprises an integrator, an analog-to-digital converter, and a controller. An input signal is received by the integrator to generate an integrated signal. The integrated signal is then converted by the analog-to-digital converter into a digital modulation signal. The input signal is received by the controller to calculate an input signal power. The analog-to-digital converter can be controlled by the controller based on a predetermined power value and a sum of the input signal power and a total quantization error power. By the way mentioned above, the out rate of the sigma-delta modulator is reduced.

Sigma-delta modulator and an output rate reduction method thereof

A signal processing system for changing a level of an input signal to generate an output signal is disclosed. The signal processing system includes a shifter, a sigma-delta modulator, and a level adjuster. The shifter is utilized for receiving the input signal and for bit-shifting the input signal according to a first predetermined gain to generate a first adjustment signal. The sigma-delta modulator is utilized for generating the output signal according a second adjustment signal and the first adjustment. The level adjuster is utilized for adjusting a level of the output signal according to a second predetermined gain to generate the second adjustment signal.

Signal processing system capable of changing signal levels

A fractional frequency synthesizer, applied to a phase-locked loop, includes a phase detector, a loop filter, a controllable oscillator, a first frequency divider, and a sigma-delta modulator (SDM). The phase detector generates a phase difference signal according to a reference signal and a feedback signal. The loop filter filters the phase difference signal to generate a filtered signal. The controllable oscillator generates the frequency signal according to the filtered signal. The first frequency divider generates the feedback signal by dividing a frequency of the frequency signal according to a dividing factor. The SDM determines the dividing factor according to a control signal.

Fractional frequency synthesizer and phase locked loop utilizing fractional frequency synthesizer and method thereof

An apparatus includes a first trigger, a second trigger, a pulse generator, and a control unit. The first trigger generates a first trigger signal and a first level signal; the second trigger generates a second trigger signal and a second level signal; the pulse generator generates a digital output signal according to the first and the second level signals; and the control unit outputs the first and the second control voltages according to the digital input signal and the digital output signal.

Digital amplifier and method thereof

A sigma-delta modulator is disclosed. The sigma-delta modulator includes a first integrator, a second integrator, an analog-to-digital converter, a digital-to-analog converter (DAC), and a compensating device. The first integrator receives an input signal for generating a first output signal. The second integrator receives the first output signal for generating a second output signal. The ADC converts the second output signal into a digital modulation signal. The DAC converts the digital modulation signal into an analog feedback signal. The analog feedback signal is transmitted to the first integrator and the second integrator. The compensating device is for compensating the analog feedback signal for a time delay caused by a feedback loop from the ADC through the DAC to the first integrator.

Sigma-delta modulator capable of compensating a time delay

A reference voltage generating circuit includes a first capacitor having a first end and a second end; a second capacitor having a third end and a fourth end; a first switch for selectively coupling a predetermined voltage to the first end of the first capacitor; a second switch for selectively coupling the third end of the second capacitor to the first end of the first capacitor; a third switch for selectively coupling the first end of the first capacitor to a reference voltage level; and a fourth switch for selectively coupling the second end of the first capacitor to a reference voltage level; wherein the first capacitor samples the predetermined voltage in a first stage and re-distributes charges to the second capacitor in a second stage.

Reference voltage generating circuit

An amplifier includes a subtracting unit for generating an error signal according to an input signal and an output signal; a noise shaping unit for executing a noise shaping operation on the error signal to produce a noise-shaped signal; a pulse adjustment unit for generating a control signal according to the noise-shaped signal and the input signal; and a power stage for generating the output signal according to the control signal.

Power amplifier and method for error correcting of output signals thereof

An application circuit for shaping noises and method thereof involve an analog-to-digital converter which converts a first analog signal into an n-bit digital signal for an encoder to generate a p-bit digital signal. Then a control circuit generates a plurality of control signals based on the p-bit digital signal, wherein p is two to the power of n minus one, and n is an integer greater than one. Each of the (2&#x2212;1) unit elements with element mismatch in an internal n-bit digital-to-analog converter executes the digital to analog conversion in response to the corresponding control signal, thereby generating a second analog signal, and an adder outputs the first analog signal based on the second analog signal and a third analog signal.

Application circuit and method for shaping noises

An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.

High voltage tolerance output stage

A reference voltage generating circuit includes: a first capacitor; a second capacitor; a reference voltage sampling capacitor; a first switch for alternatively coupling the second capacitor to a predetermined voltage to allow the second capacitor to sample the predetermined voltage; a second switch for alternatively coupling the second capacitor to the first capacitor to allow the second capacitor to redistribute charges with the first capacitor in order to generate the reference voltage; and a third switch for alternatively coupling the first capacitor to the reference voltage sampling capacitor to allow the reference voltage sampling capacitor to redistribute charges with the first capacitor in order to output the reference voltage.

An Audio Codec which comprises a power selecting circuit an audio compiler circuit and a control amplifier circuit. The power selecting circuit receives at least a primary power source and an auxiliary power source and outputs a working power selected from the power sources. The auxiliary power source is selected and output to the control amplifier circuit only when the computer is at a power-off status. When the computer is power-on, the primary power source will be selected and output to both the audio compiler circuit and the control amplifier circuit. Therefore, the Audio Codec of the present invention only needs one set of internally furnished control amplifier circuit to both operate on the normal power-on status and perform the Power OFF CD function.

Audio control device

An audio converting device including a digital high-pass filter, an expander, a digital low-pass filter, a delta-sigma modulator, a digital-to-analog converter, an analog low-pass filter and a gain control unit is provided. The digital high-pass filter in this invention can filter out a direct-current component of digital audio data such that the production of noise is avoided when the volume is adjusted by users.

Audio converting device and converting method thereof

An amplifier circuit having a high time constant. An operational amplifier includes a non-converting input terminal coupled to a ground, a converting input terminal and an output terminal. A first resistor network including at least one stage is coupled between the converting input terminal and the output terminal. Each stage of the first resistor network includes a first node, a first current path and a second current path connected to the first node. The first current path of each stage of the first resistor network is connected to the first node of the next stage, the second current path of each stage of the first resistor network is grounded, and the first current path of the first stage of the first resistor network is connected to the converting input terminal. A loading unit is coupled between the converting input terminal and the output terminal.

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Yun-Lin Hsien, Taiwan

Wen-Chi Wang