Taiwan Semiconductor Manufacturing Comp. Ltd.

Wen-Chen Lu

Shih-Chi Fu

Ching-Sen Kuo

Kai Tzeng

Feng-Jia Shiu

Yi-Min Chen

Ming-Chang Hsieh

Ying-Hua Chen

Ming-Ying Hsieh

Hua-Tai Lin

Hau-Yan Lu

Ming-Hui Chih

Chien-Wen Lai

Chin-Min Huang

Chia-Cheng Chang

Cherng-Shyan Tsay

Hung-Wen Cho

Chih-Yuan Chen

Chen-Yan Li

Chaos Tsai

Jau-Shian Liang

A method for fabricating a photonic package device is provided. The method includes patterning a semiconductor layer of a semiconductor-on-insulator (SOI) substrate into a waveguide structure and at least one first semiconductor pillar; forming a metal-dielectric stack over the waveguide structure and the first semiconductor pillar; etching an opening in the metal-dielectric stack to expose the first semiconductor pillar; etching an insulator layer of the SOI substrate to form at least one insulator cap below the first semiconductor pillar; and etching a base semiconductor substrate of the SOI substrate to form at least one second semiconductor pillar below the insulator cap.

Photonic package device and method for fabricating the same

In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a CMP stop layer is formed over the first ILD layer, a trench opening is formed by patterning the CMP stop layer and the first ILD layer, an underlying first process mark is formed by forming a first conductive layer in the trench opening, a lower dielectric layer is formed over the underlying first process mark, a middle dielectric layer is formed over the lower dielectric layer, an upper dielectric layer is formed over the middle dielectric layer, a planarization operation is performed on the upper, middle and lower dielectric layers so that a part of the middle dielectric layer remains over the underlying first process mark, and a second process mark by the lower dielectric layer is formed by removing the remaining part of the middle dielectric layer.

Methods of manufacturing semiconductor device and semiconductor device

In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

Method (and related apparatus) that reduces cycle time for forming large field integrated circuits

A method includes receiving an integrated circuit (IC) layout having a pattern layer. The pattern layer includes a main layout pattern. A dimension Wof the main layout pattern along a first direction is greater than a wafer metrology tool's critical dimension (CD) measurement upper limit. The method further includes adding a plurality of assistant layout patterns into the pattern layer. The plurality of assistant layout patterns includes a pair of CD assistant layout patterns on both sides of the main layout pattern along the first direction. The pair of CD assistant layout patterns have a substantially same dimension Walong the first direction and are about equally distanced from the main layout pattern by a dimension D. The dimensions Wand Dare greater than a printing resolution in a photolithography process and are equal to or less than the wafer metrology tool's CD measurement upper limit.

Assistant pattern for measuring critical dimension of main pattern in semiconductor manufacturing

A method of forming of an image sensor device includes a patterned hardmask layer is formed over a substrate. The patterned hard mask layer has a plurality of first openings in a periphery region, and a plurality of second openings in a pixel region. A first patterned mask layer is formed over the pixel region to expose the periphery region. A plurality of first trenches is etched into the substrate in the periphery region. Each first trench, each first opening and each second opening are filled with a dielectric material. A second patterned mask layer is formed over the periphery region to expose the pixel region. The dielectric material in each second opening over the pixel region is removed. A plurality of dopants is implanted through each second opening to form various doped isolation features in the pixel region.

Image device and methods of forming the same

A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements, wherein a top portion of the deep doped region is below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with the top portion of the deep doped region.

Method of preparing self-aligned isolation regions between sensor elements

A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate. The method includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements and starting at a distance below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with a top portion of the deep doped region.

Self-aligned implants to reduce cross-talk of imaging sensors

The present disclosure relates to a method of performing an optical proximity correction (OPC) procedure that provides for a high degree of freedom by using an approximation design layer. In some embodiments, the method is performed by forming an integrated chip (IC) design having an original design layer with one or more original design shapes. An approximation design layer, which is different from the original design layer, is generated from the original design layer. The approximation design layer is a design layer that has been adjusted to remove features that may cause optical proximity correction (OPC) problems. An optical proximity correction (OPC) procedure is then performed on the approximation design layer. By performing the OPC procedure on the approximation design layer rather than on the original design layer, characteristics of the OPC procedure can be improved.

OPC method with higher degree of freedom

Methods of forming self-aligned patterns for performing oppositely doped deep implantations in a semiconductor substrate are disclosed. The semiconductor substrate has implantation and non-implantation regions. The methods include forming a hardmask pattern for a first implantation with a first conductivity-type dopant, depositing an etch stop layer, filling trenches between the hardmask pattern with a sacrificial filler material having a higher wet etch resistance than the hardmask, removing a top portion of the sacrificial filler material and the etch stop layer over a top surface of the hardmask pattern, removing the hardmask pattern in the implantation region by wet etching, and performing a second ion implantation with a second conductivity type dopant opposite of the first conductivity type.

Self-aligned patterning for deep implantation in a semiconductor structure

A sensor array is integrated onto the same chip as core logic. The sensor array uses a first polysilicon and the core logic uses a second polysilicon. The first polysilicon is etched to provide a tapered profile edge in the interface between the sensor array and the core logic regions to avoid an excessive step. Amorphous carbon can be deposited over the interface region without formation of voids, thus providing for improved manufacturing yield and reliability.

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Kaohsiung, Taiwan

Wen-Chen Lu