Realtek Semiconductor Inc.

Wen-Che Wu

Wen-Hsia Kung

Hsien-Chun Chang

Yi-Shu Chang

Wen-Jui Lin

Yu-Pin Chou

Hsin-Hung Yi

A control device for three dimensional display has an image processor and a timing signal generator. The image processor is used for receiving a first and a second input image signals to generate a first, a second, and a third output image signals. The first output image signal comprises part of the first input image signal. The second output image signal comprises part of the first input image signal and part of the second input image signal. The third output image signal comprises part of the second input image signal. The timing signal generator is used for generating a first lens control signal for configuring a first lens to be non-opaque when the second output image signal is displayed on a display device, and generating a second lens control signal for configuring a second lens to be non-opaque when the third output image signal is displayed on the display device.

Device and method for 3-D display control

A controller and a method of updating parameters on the same. The controller includes an embedded non-volatile memory, a programming circuit, an embedded SRAM, a MCU (Micro Computer Unit), and a memory controller. The embedded non-volatile memory has a program code block for storing program codes to be executed by the MCU, and a data block for storing the parameters. The MCU writes the parameters into the data block of the flash memory through the memory controller, or reads data in the data block of the non-volatile memory through the memory controller. Because the controller does not need to employ an external EEPROM, the cost can be reduced and the speed for accessing the parameters can be increased.

Display controller having an embedded non-volatile memory divided into a program code block and a data block and method for updating parameters of the same

The present invention discloses a circuit and a method of adjusting system clock in low voltage detection, and a low voltage reset circuit. The circuit of adjusting system clock in low voltage detection comprises: a clock generator for supplying a clock to at least one circuit in a system; and a low voltage reset circuit for generating an adjustment signal according to a detected voltage level, so that the clock generator adjusts or stops the clock supplied to the at least one circuit in the system.

Circuit and method of adjusting system clock in low voltage detection, and low voltage reset circuit

A representative Device and Method for 3-D Display Control is disclosed. The method for controlling stereo image display is disclosed. That is, to receive an image input signal wherein the image input signal includes a first refresh rate; to convert a frame rate of the image input signal to generate an image output signal, wherein the image output signal includes a second refresh rate which is higher than the first refresh rate, and includes a first image signal, a first VBI (Vertical Blanking Interval), a second image signal, a second VBI, a third image signal and a third VBI; to output a control signal for a left eye shutter of shutter glasses during a duration between the first VBI and a part of the second image signal; and to output a control signal for a right eye shutter of the shutter glasses during a duration between a part of the third image signal and the third VBI.

A power-on reset circuit includes a clamping signal generator and a determining device. The clamping signal generator is adapted to receive a trigger signal, and generates a clamping signal with reference to the trigger signal. The clamping signal generator includes an output unit for generating the clamping signal according to a feedback signal, and a feedback unit for generating the feedback signal according to first and second intermediate signals. The first intermediate signal is generated with reference to the clamping signal. The second intermediate signal is generated according to the trigger signal. The determining device is adapted to receive the trigger signal, is coupled to the clamping signal generator for receiving the clamping signal therefrom, and is operable to generate a reset signal according to the trigger signal and the clamping signal.

Power-on reset circuit

An interface transmission device and method are disclosed. The interface device, located in a first device, includes a transmission interface and a receiving circuit. The transmission interface receives an initialization signal and an interface signal. The receiving circuit receives the initialization signal through the transmission interface, and acquires a bit length of the interface signal according to the initialization signal. Thereby, the first device resolves the interface signal according to the bit length.

Interface transmission device and method

The invention provides an image encoding/decoding device and method. An encoding/decoding architecture of the invention includes: encoders for encoding image data into data blocks; a reordering multiplexer for receiving the data blocks and determining an order by which the data blocks are written into a memory according to an order of an achieved percentage of an encoding progress for each encoder; a memory writing unit, a memory dispatcher, a memory controller, and a memory reading unit, for writing the data blocks into the memory and reading the data blocks from the memory; a request demultiplexer for receiving the read data blocks from the memory reading unit and outputting the received data blocks according to data request signals; and decoders for generating the data request signals, receiving the output data blocks from the request demultiplexer, decoding the received data blocks, and then outputting the decoded data blocks.

Image encoding/decoding device and method thereof with data blocks in a determined order

A system for programming at least a controller chip is disclosed. The system includes a programming apparatus and at least a programmable device mounted on the programming apparatus. The programming apparatus has at least a first connection interface and a micro-controller. The programmable device has the monitor controller chip mounted thereon and a second connection interface coupled between the first connection interface and the controller chip. The micro-controller controls the programming of the controller chip.

Growing community of inventors

Hsinchu County, Taiwan

Wen-Che Wu