Mediatek Singapore Pte. Ltd.

Mediatek Corporation

Wen-Chang Lee

Xiaochuan Guo

Augusto Marques

Caiyi Wang

Yen-Horng Chen

Jenwei Ko

Chii-Horng Chen

Hsin-Hung Chen

Ping-Ying Wang

Chih-Yuan Lin

Po-Sen Tseng

Shih-Chi Shen

Wei-Hsin Tseng

Ming-Chou Wu

Narayanan Baskaran

Chieh-Hsun Hsiao

Changhua Cao

A transmission interface between at least a master module and a slave module is proposed. The transmission interface includes a predetermined number of physical transmission medium(s). Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated, and the predetermined number is not smaller than a number of intermediate frequency (IF) stream(s) to be transmitted.

Method for transferring signals via transmission interface and communications apparatus utilizing the same

A class-F power amplifier (PA) with a matching network is disclosed herein. The class-F PA comprises a first switch and a second switch operating in differential mode, with a second harmonic trap circuitry selectively terminating the drain terminals to ground at a second harmonic frequency. The second harmonic trap circuitry comprises a plurality of lumped inductive and capacitive components. The PA further comprises a common mode trap and a matching network to reduce the imbalance of the drain terminal impedance between first harmonics and third harmonics.

Class-F power amplifier matching network

A digitally-controlled oscillator (DCO) includes a first capacitor array and a second capacitor array responsive to an integer part and a fractional part of a digital control word, respectively. The mismatch measurement of the DCO includes a first settling phase and a second settling phase. In the first settling phase, the first capacitor array is fixed to have one capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to a target value. In the second settling phase, the first capacitor array is fixed to have another capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to the same target value. The capacitor mismatches are estimated according to characteristic values derived from the digital control word adaptively adjusted in the first setting phase and the second setting phase.

Method and apparatus for measuring/compensating mismatches in digitally-controlled oscillator

A tunable inductor includes a main wiring and at least one tuning module. The main wiring is arranged to encircle an inductor area of the tunable inductor. In addition, the tuning module is arranged to couple associated nodes of the main wiring. For example, each tuning module of the at least one tuning module includes a first switch positioned within the inductor area, and further includes at least one auxiliary wiring. When the first switch is turned on, the tuning module couples two nodes of the main wiring, where the at least one auxiliary wiring is arranged to couple the two nodes when the first switch is turned on. In particular, a patterned ground plane is arranged to decrease the energy loss of the tunable inductor, and more particularly, to prevent the tunable inductor from suffering energy loss. The patterned ground plane includes some conductive sections forming a W-like shape.

Tunable inductor

A calibration device arranged for calibrating an oscillating frequency of an oscillator includes: a phase locking device arranged to track a first reference clock generated by the oscillator until a feedback clock is phase-aligned with the first reference clock, and then arranged to track a second reference clock generated by the oscillator until a phase difference between the second reference clock and the feedback clock is a static phase difference, wherein the feedback clock is generated by dividing an output oscillating signal of the phase locking device by a divisor; an adjusting circuit arranged to adjust the divisor into an updated divisor to reduce the static phase difference between the second reference clock and the feedback clock; and a calibrating circuit arranged to calibrate the oscillating frequency of the oscillator according to the updated divisor, wherein the second reference clock is generated by varying a control signal of the oscillator.

Calibration device for oscillator and method thereof

A clock generating apparatus includes: a time-to-digital converter (TDC) arranged to convert a timing difference between a reference clock and a variable clock to generate a digital value; a calibrating device arranged to generate a control signal according to the digital value and the reference clock; a controllable oscillator arranged to generate an oscillating signal according to the control signal and the digital value; and a feedback device arranged to generate the variable clock to the TDC according to the oscillating signal, and the calibrating device calibrates the controllable oscillator to make the oscillating signal have a target oscillating frequency.

Clock generating apparatus and frequency calibrating method of the clock generating apparatus

A digitally controlled oscillator is provided. The digitally controlled oscillator includes a pair of transistors cross-coupled to each other, a switched capacitor array coupled to the pair of transistors and a plurality of frequency tracking units coupled to the pair of transistors. The pair of transistors provides an output signal. The switched capacitor array tunes a frequency of the output signal. The frequency tracking units tune the frequency of the output signal to a target frequency. At least one of the frequency tracking units is capable of selectively providing a first capacitance and a second capacitance. A tuning resolution of the frequency tracking unit is determined by a difference between the first and second capacitances.

Digitally controlled oscillator

One exemplary tunable capacitive device includes a first tunable capacitive element, a first coupling capacitive element, a first coupling resistive element, and a first specific capacitive element. The first tunable capacitive element has a first node coupled to a first input voltage, and a second node. The first coupling capacitive element has a first node coupled to the second node of the first tunable capacitive element, and a second node coupled to a first connection terminal of the tunable capacitive device. The first coupling resistive element has a first node coupled to the second node of the first tunable capacitive element, and a second node coupled to a second input voltage, where the first input voltage and the second input voltage include a control voltage and a reference voltage. The first specific capacitive element is coupled between the first node and the second node of the first tunable capacitive element.

Growing community of inventors

Taipei, Taiwan

Wen-Chang Lee