Taiwan Semiconductor Manufacturing Comp. Ltd.

Wen-Chang Cheng

Yi-Ching Liu

Chieh Lee

Yih Wang

Jonathan Tsung-Yung Chang

Chia-En Huang

Chia-en Huang

A memory device including a memory array configured to store data, a sense amplifier circuit coupled to the memory array, and a read circuit coupled to the sense amplifier circuit, wherein the read circuit includes a first input that receives a read column select signal for activating the read circuit to read the data out of the memory array through the read circuit during a read operation.

Sense amplifier with read circuit for compute-in-memory

A memory structure includes a first memory array having bit lines; a second memory array having bit lines; a first sense amplifier connected to a first bit line of the first memory array and a first bit line of the second memory array; and a second sense amplifier connected to a second bit line of the first memory array and a second bit line of the second memory array. The second bit line of the first memory array is adjacent to the first bit line of the first memory array, and the second bit line of the second memory array is adjacent to the first bit line of the second memory array.

Memory circuits, memory structures, and methods for fabricating a memory device

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Richmond, TX, United States of America

Wen-Chang Cheng