Taiwan Semiconductor Manufacturing Comp. Ltd.

Wen-Chan Lin

Chue-San Yoo

Yuan-Chang Huang

Cheng-Yeh Shih

A method for making improved capacitor bottom electrodes (capacitor nodes) having longer refresh cycle times and increased capacitance for DRAM cells has been achieved. The method involves using a polysilicon high-temperature film (HTF) instead of the conventional doped polysilicon to form the node capacitors. After forming the DRAM pass transistors (FETs) and depositing an insulating layer, node contact openings are etched in the insulator to the drain of the FET. The capacitor bottom electrodes are formed by depositing a polysilicon HTF at a temperature of at least 650.degree. C. using a reactant gas mixture of H.sub.2 /SiH.sub.4 /PH.sub.3, which results in a longer refresh cycle time and increased capacitance. This results in a significantly improved final die yield. After forming an interelectrode dielectric layer on the bottom electrodes, another doped polysilicon layer is deposited to form the top electrodes to complete the DRAM cells.

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Hsin-Chu, Taiwan

Wen-Chan Lin