Macronix International Co., Ltd.

Wen-Bin Tsai

Chun-Pei Wu

Huei-Huang Chen

Ching-Yu Chang

Samuel C Pan

Huei-Huarng Chen

Hsuan-Ling Kao

Hui-Huang Chen

A flash memory includes substrate, control gates, trenches, source regions, isolation structures, drain regions, a common source line, floating gates, tunneling dielectric layers, and dielectric layer. The control gates and the trenches are in first and second directions on the substrate, respectively. The source regions are in the substrate and trenches on one side of control gates. The isolation structures fill the trenches between the source regions. The drain regions are in the substrate on the other side of control gates between the isolation structures. The common source line is in the second direction inside the substrate and electrically connected to the source regions. Furthermore, the floating gates are between the control gates and the substrate that between the source and drain regions. The tunneling dielectric layers are disposed between the floating gates and the substrate, and the dielectric layer is disposed between the floating and control gates.

Flash memory with a trench common source line

A method for fabricating a mask read-only-memory with diode cells is provided. A doped conductive layer with a first conductivity is formed on bit lines. Then, a photoresist layer with a mask ROM pattern is formed on an interlayer dielectric layer on the doped conductive layer for serving as an etching mask, thereby forming openings in the interlayer dielectric layer unto the exposed regions of the doped conductive layer. Performing ion implantation to form a diffusion region with a second conductivity opposite to the first conductivity in each exposed region of the doped conductive layer, so that the doped conductive layer and the diffusion regions formed therein constitute diode cells that are served as memory cells. A contact plug is formed in each opening unto the diode cell and a conductive layer is formed on the contact plug for serving as word lines.

Method for fabricating a mask read-only-memory with diode cells

A planarization method using anisotropic etching can be applied to planarize an insulating layer with an uneven surface on a substrate. H SO , H PO , HF and H O are mixed to form an etching solution. The substrate is placed into the etching solution to make the etching solution pass the surface of the insulating layer at a flow rate to etch the insulating layer. After a period of etching time, the insulating layer with a more planar surface can be obtained.

Planarization method using anisotropic wet etching

A process for fabricating a sharp corner-free shallow trench isolation structure. First, a SiON layer and a mask layer are successively formed on a semiconductor substrate. The SiON layer and mask layer are patterned to form an opening, exposing the substrate region on which a shallow trench isolation region will be formed. Next, an oxide spacer is formed on sidewalls of the SiON layer and mask layer. A trench is formed in the semiconductor substrate using the spacer and mask layer as a mask. Next, a liner oxide layer is formed on the surface of the trench by thermal oxidation, such that the liner oxide layer near the SiON layer is in a bird's beak form. An isolating oxide layer is filled in the trench. Finally, the mask layer and SiON layer are removed. The present invention forms a short and thick bird's beak structure and rounded trench corner. Therefore, the thickness of the tunnel oxide is even and the tunnel oxide integrity remains. Thus, the electric current is not accumulated on the trench corner, and parasitic transistors and current leakage can be prevented.

Growing community of inventors

Tainan, Taiwan

Wen-Bin Tsai