United Microelectronics Corp.

Wen-Bin Shieh

Water Lur

Chih-Chien Liu

Juan-Yuan Wu

Shih-Wei Sun

Ta-Shan Tseng

Chih-Hsing Hsin

A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

High density plasma chemical vapor deposition process

A vernier having multi-pitch for checking alignment accuracy. The vernier has the same pitch as the line width of the IC pattern where the diffraction angle of the vernier is the same as that of the IC pattern. The pitch comprises slits which cannot produce image on the wafer, such that a simultaneous pattern with the conventional pattern on the wafer is formed. Accordingly, the alignment accuracy can be accurately checked, thereby monitoring the alignment of IC patterns.

Multi-pitch vernier for checking alignment accuracy

Disclosed is a template and a method for using the template for focus control of pattern definition image in lithographic process, particularly for IC production. The template has at least a serrated vernier and at least a rhombus printed thereon. In use, the template is mounted on a mask used for pattern definition during a lithographic process. Upon development of a wafer image of the mask, in the normal course of lithography, there is also visible on the wafer an image of the template. This image, particularly the rhombus pattern, can be easily visually inspected by quality control personnel. The rhombus pattern shows a defocus condition because its normally straight and parallel sides and corners show a roundness even with the slightest defocus. Wafers that have not been properly imaged during lithography can be discarded without wasting further process steps in IC production to enhance yield.

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Hsin-Chu, Taiwan

Wen-Bin Shieh