Lam Research Corporation

Wen-Ben Chou

Rajinder Dhindsa

Roger Patrick

Ching-Hwa Chen

Thomas D Nguyen

Phillip Lawrence Jones

Yun-Yen Jack Yang

Shih-Yuan Cheng

Guang-Yaw Hwang

Yu-Wei Yang

Wayne Tu

Kambiz Fallahpour

Timothy Tran

A method for etching a barrier material on a semiconductor substrate is disclosed. The method includes placing the substrate in a plasma processing chamber of the plasma processing system, wherein the substrate includes the barrier material and a low-k material, and wherein the barrier material and a low-k material are configured to be exposed to a plasma. The method also includes flowing an etchant gas mixture, including CHF from about 4% to about 8% of a plasma gas flow, into the plasma processing chamber, wherein the etchant gas mixture is configured to etch the barrier material at a first etch rate, the etchant gas mixture is configured to etch the low-k material at a second etch rate, wherein the first etch rate is substantially greater than the second etch rate. The method further includes striking a plasma from the etchant source gas; and etching the barrier layer and the low-k layer.

Methods and apparatus for the optimization of highly selective process gases

A method for fabricating a spacer of a gate structure is provided. The method performing a first etch process implementing a first etchant gas. The first etch process is configured to implement an interferometry endpoint (IEP) detection method to detect a removal of a portion of a spacer layer having a specific thickness from over the surface of the substrate, thus leaving a thin spacer layer. The method further includes performing a second etch process for a predetermined period of time implementing a second etchant gas. The second etch process is configured to remove the thin spacer layer, leaving the spacer for the gate structure.

Method and apparatus for nitride spacer etch process implementing in situ interferometry endpoint detection and non-interferometry endpoint monitoring

A method of cleanly etching an organic polymer layer disposed over a substrate is disclosed. The invention is particularly useful in damascene processing where openings are etched in the organic polymer layer to form interconnects. The method includes lowering the temperature of the substrate. The method also includes flowing H O vapor over the organic polymer layer and condensing (or freezing) the H O vapor on the organic polymer layer. The method additionally includes etching through the organic polymer layer and the condensed H O vapor to form an opening having a side wall. The condensed (or frozen) H O vapor is arranged to form a passivating film (of ice) along the side wall of the opening to protect the side wall from etching.

Clean chemistry low-k organic polymer etch

An apparatus and method in a plasma processing chamber for reducing charging of a wafer is described. A plasma generating element is configured to cause a plasma including ions and free radicals to be formed in a plasma generating region. A plasma diffusion region is configured so that plasma generated in the plasma generating region can diffuse through the plasma diffusion region. A conductive grid is positioned within the plasma diffusion region between the wafer and the plasma generating region. The conductive grid includes a mesh which is configured to trap a portion of the ions so that a portion of the ions are prevented from diffusing through the diffusion region to reach the wafer.

Methods and apparatus for reducing charging during plasma processing

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Palo Alto, CA, United States of America

Wen-Ben Chou