Western Digital Technologies, Inc.

Hgst Netherlands, B.v.

International Business Machines Corporation

Hitachi Global Storage Technologies Netherlands B.v.

Weldon Mark Hanson

Richard Leo Galbraith

Niranjay Ravindran

Iouri Oboukhov

Travis Roger Oenning

Derrick E Burton

Roger William Wood

Jonas Andrew Goode

Evangelos Stavros Eleftheriou

Roy Daron Cideciyan

Thomas Mittelholzer

John Thomas Contreras

Ajay Dholakia

Pradhan Bellam

Jonathan Darrel Coker

Alexander M Taratorin

David Timothy Flynn

Guoxiao Guo

Martin Aureliano Hassner

Satoshi Yamamoto

Joey Martin Poss

Rehan Ahmed Zakai

Alain Chahwan

Charles A Park

Samir Y Garzon

Duc H Banh

David James Stanek

Michael Joseph Ross

Todd Carter Truax

David Scott C Amiss

Srinivasan Surendran

Erhard Theodor Schreck

Barry C Stipe

Yuan Xing Lee

Daniel Bedau

James N Malina

Sukumar Rajauria

Hideki Zaitsu

Fuminori Sai

Xiaodong Che

Michael Paul Salo

Zarko Popov

Thomas C Christensen

Mark A Nichols

Kazuhiro Saito

Henry Yip

Donald Earl Vosberg

Kraig Bottemiller

Gary William Walker

Hiroyasu Masuda

So Ogiwara

James Joseph Mosser

Yeoungchin Yoon

Toshihisa Komai

Michael J Ross

Example systems and methods for using synchronization marks to correct insertions and deletions for DNA data storage are described. A data unit may be encoded in oligos that include synchronization marks at predetermined intervals along the length of each oligo. During decoding, the synchronization marks may improve identification and isolation of insertions and deletions for correction of symbol alignment prior to error correction code decoding. In some configurations, correlation analysis may be used to improve isolation of insertions and deletions where multiple copies of the same oligo are available.

Preprocessing for correcting insertions and deletions in DNA data storage

Example channel circuits, data storage devices, and methods for asynchronous sampling from an oversampled analog-to-digital converter are described. The channel circuit may include an analog-to-digital converter configured to generate an oversampled digital signal from an analog data signal using a sample rate that is an integer multiple of the baud rate of the channel circuit. A digital sample interpolator may then interpolate interpolated digital signal values from multiple signal values of the oversampled digital signal and select values at baud rate to generate a baud rate digital signal. The baud rate digital signal may be used by an iterative detector in a timing loop and, once a target timing is achieved, for the iterative detector to detect data bits from the interpolated digital signal.

Channel circuit with asynchronous sampling from an oversampled analog-to-digital converter

Example systems and methods for using nested error correction codes for DNA data storage are described. A data unit may be encoded in a set of oligos. Using an error correction code, such as an LDPC code, a codeword may be determined for the data unit that is a multiple of the data payload capacity of each oligo. The codeword may be divided among the set of oligos, along with corresponding redundancy data. Any number of additional levels of nested error correction codes may be implemented by aggregating sets of smaller codewords into larger codewords and storing the corresponding redundancy data in the set of oligos. Each nested level may be aggregated from the set of oligos and decoded using the corresponding error correction code matrix and set of redundancy data as needed, such as in response to failure to decode codewords at a lower level.

Nested error correction codes for DNA data storage

Example channel circuits, data storage devices, and methods for using zero force adaptation to equalize a read data signal based on known data are described. A known user data signal may be determined during prior read operations and used with a residue term from the equalized read data signal to adapt the tap weights for an equalizer filter using a zero force adaptation algorithm. For example, the known user data signal may be determined by a soft output detector (e.g., SOVA detector) or full or partial decoding by an iterative decoder (e.g., LDPC decoder) and fed back for adapting the equalizer.

Channel circuit with zero force equalizer

Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix are described. Data units may be read from a storage medium. Multiple sets of parity bits may be available for different data units, different sets of parity bits having a different number of parity bits corresponding to different parity matrices and desired code rates. A primary parity matrix may provide a base code rate and one or more extended parity matrices may provide increased code rates based on additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data units based on the data units from the read signal.

Adjustable code rates and dynamic ECC in a data storage device

Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix based on write verification determining extended parity are described. A data unit with a base set of parity bits may be written to a non-volatile storage medium and then read back for write verification. The data unit may be decoded using the base set of parity bits and corresponding primary parity matrix. Based on the decoding of the write verification read signal, a number of parity bits for an extended set of parity bits may be determined and the extended set of parity bits may be stored to an extended parity storage location for use during subsequent read operations.

Adjustable code rates and dynamic ECC in a data storage device with write verification

Various illustrative aspects are directed to a data storage device comprising data tracks N and N−1, and one or more processing devices, configured to identify, during a track write on the data track N, a write abort event based upon an expected risk for the data track N−1 exceeding a risk threshold, read one or more sectors of the data track N−1 and collect one or more corresponding sector metrics, verify the one or more sectors based upon the collected sector metrics, wherein the verifying comprises assigning each of the one or more sectors as one of a readable or a non-readable sector, and continue the track write on the data track N upon determining each of the one or more sectors is a readable sector, or recovering and relocating the data track N−1 based on determining at least one of the sectors is a non-readable sector.

Sector metrics to estimate health of written data

Example control circuitry, data storage devices, and methods to provide a spiral data track format that is different from the underlying servo track format are described. The data storage device may include a storage medium configured with a plurality of tracks in at least one continuous spiral pattern and a head actuated over the storage medium. The data tracks may be written to the storage medium with track lengths that are different than a single revolution of the storage medium.

Offset spiral data track format for data storage devices

Example read channel circuits, data storage devices, and methods to provide overlapping processing of data tracks are described. The data storage device may include media configured with a plurality of tracks in a concentric or continuous pattern. The read signal for a data track may be processed using error correction codes (ECC) as it is read during a first track read operation period. Some portion of its data sectors may need additional ECC postprocessing after the first track is initially received and processed by the read channel circuit. While the read signal for a next data track is being read and processed, the read channel circuit may continue postprocessing of the portion of data sectors from the first track during the second track read operations. Various decision parameters for managing the data stream, additional postprocessing time, and rereading tracks for data recovery are also described.

Overlapping processing of data tracks

Example systems, read channels, and methods provide bit value detection from an encoded data signal using a neural network soft information detector. The neural network detector determines a set of probabilities for possible states of a data symbol from the encoded data signal. A soft output detector uses the set of probabilities for possible states of the data symbol to determine a set of bit probabilities that are iteratively exchanged as extrinsic information with an iterative decoder for making decoding decisions. The iterative decoder outputs decoded bit values for a data unit that includes the data symbol.

Neural network soft information detector in a read channel

Example channel circuits, data storage devices, and methods for using an extendable parity code matrix are described. A data unit may be read from a storage medium. Multiple sets of parity bits may be available for the data unit, each set of parity bits having a different number of parity bits corresponding to different parity matrices, including a primary parity matrix and at least one extended parity matrix. The extended parity matrix includes the primary parity matrix and additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data unit based on the data unit from the read signal.

Extendable parity code matrix construction and utilization in a data storage device

Various illustrative aspects are directed to a data storage device comprising data tracks N and N&#x2212;1, and one or more processing devices, configured to measure signal to noise ratio (SNR) metrics for corresponding sectors of at least one of the data tracks N&#x2212;1 and N, where the measuring is based at least in part on reading one or more of the data tracks N and N&#x2212;1 using one or more read offsets, estimate a position of at least one of the data tracks based on measuring the one or more SNR metrics, and reconstruct one or more of risk values for at least a portion of the data track N&#x2212;1 based on the one or more SNR metrics for the data track N&#x2212;1, and a position error signal (PES) for at least one of the data tracks N&#x2212;1 and N based on the corresponding estimated positions.

Position and risk reconstruction in shingled magnetic recording data storage devices

Example systems, read channel circuits, data storage devices, and methods to provide signal correction based on soft information in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, and a signal correction circuit. The soft output detector passes detected data bits and corresponding soft information to the signal correction circuit. The signal correction circuit uses the soft information to determine a signal correction value, which is combined with input signal to return a corrected signal to the soft output detector for a next iteration. In some configurations, the signal correction value may compensate for DC offset, AC coupling poles, and/or signal asymmetries to reduce baseline wander in the read channel.

Signal correction using soft information in a data channel

A data storage device is disclosed comprising a head actuated over a magnetic media comprising a plurality of tracks. A first pattern of magnetic transitions is written to a first segment of a first track. Preparation is made to write a second pattern of magnetic transitions to a second segment of a second track adjacent the first segment of the first track. When the second pattern matches the first pattern, a write boost is configured to a first setting, and when the second pattern does not match the first pattern, the write boost is configured to a second setting. The second pattern of magnetic transitions is then written to the second segment of the second track using the configured write boost.

Data storage device with history dependent write boost

A data storage device configured to access a magnetic tape is disclosed comprising a plurality of data tracks. A first head is configured to access a first data track comprising a first sync mark, and a second head is configured to access a second data track comprising a second sync mark. The first head is used to read first data from the first data track, wherein the first data comprises a plurality of symbols, and the second head is used to read the second sync mark from the second data track. The first data is symbol synchronized based on the second head reading the second sync mark from the second data track.

Data storage device synchronizing first channel based on sync mark detected in second channel

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Rochester, MN, United States of America

Weldon Mark Hanson