Altera Corporation

Weizhong Xu

Yu Ying Ong

Bonnie I Wang

Gordon Raymond Chiu

Sean Shau-Tu Lu

Warren Nordyke

An integrated circuit may include a memory controller that interfaces with memory that operates using a memory clock signal having repeating memory clock cycles. The memory controller may include controller circuitry that receives memory access requests and generates corresponding memory commands using a controller clock signal having repeating controller clock cycles. The controller circuitry may partition each controller clock cycle into time slots that are associated with respective memory clock cycles. Each generated memory command may require a corresponding number of memory clock cycles to fulfill using the memory. The controller circuitry may assign a time slot to each memory command while preventing conflicts with previously issued memory commands.

Integrated circuits with improved memory controllers

A programmable integrated circuit with memory interface circuitry is provided. The memory interface circuitry may include soft memory interface logic and hard memory interface logic. The soft memory interface logic may be implemented using programmable circuits, whereas the hard memory interface logic may be implemented using non-programmable dedicated circuits. The soft memory interface logic may include error correction code (ECC) encoder and decoder circuits and circuitry for carrying out a read modified write (RMW) operation. The hard memory interface logic may include a write data buffer, a read data buffer, and other circuitry for supporting the RMW operation. The soft memory interface logic is interposed between the hard memory interface logic and the user logic on the programmable integrated circuit.

Memory interface with hybrid error detection circuitry for modular designs

An integrated circuit such as a programmable integrated circuit may include input-output circuits each having respective memory controller circuitry. The memory controller circuitry of the input-output circuits may be electrically coupled via a backbone path and configured to collectively form a memory controller. Each memory controller circuitry may include a protocol control circuit and input-output lanes. Memory access requests from on-chip circuitry may be provided to only a selected input-output circuit. The protocol control circuit of the selected input-output circuit may receive the memory access requests and generate memory control signals and local control signals from the memory access requests. The memory control signals may be provided to external memory. The local control signals may be provided to input-output circuits over the backbone path and synchronize the input-output circuits in conveying data between the integrated circuit and the external memory.

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Cupertino, CA, United States of America

Weizhong Xu