Advanced Micro Devices Corporation

USA As Represented by Secretary of the Navy

Weizhong Wang

Jayendra D Bhakta

Lei Wang

Zicheng Gary Ling

Eric Richard Kent

Warren T Yu

John Melngailis

Marty Peckerar

Critical dimension variation of photolithographically formed features on a semiconductor substrate is reduced by measuring the reflectivity of a photoresist layer and an underlying layer, such as a polysilicon layer, and adjusting the exposure level of the photoresist in accordance with the measured reflectivity. This allows precise control of feature width on the photoresist, which in turn allows precision etching of the underlying layer to accurately form a feature, such as a gate electrode.

Exposure correction based on reflective index for photolithographic process control

The present invention compactly fabricates integrated circuits of an electronic system on a semiconductor wafer by fabricating the integrated circuits of the electronic system on both sides of a semiconductor wafer. A first face of an area of the semiconductor wafer is processed with an integrated circuit fabrication process step to fabricate part of a first integrated circuit thereon. In addition, a second face of the area of the semiconductor wafer is processed with the integrated circuit fabrication process step to fabricate part of a second integrated circuit thereon. The first face and the second face are processed for a plurality of integrated circuit fabrication process steps until the first integrated circuit is completely fabricated on the first face and the second integrated circuit is completely fabricated on the second face. The first face and the second face of the area of the semiconductor wafer may both be processed simultaneously or may be processed one face at a time depending on the fabrication process step. That area of the semiconductor wafer is then cut from the rest of the semiconductor wafer such that the first integrated circuit and the second integrated circuit are on a die to be used within an electronic system. The present invention may be used to particular advantage when the first integrated circuit includes at least one processor and when the second integrated circuit includes at least one processor. In that case, the die having the first integrated circuit and the second integrated circuit is used within a multiprocessor system. With the present invention, integrated circuits of an electronic system are compactly fabricated onto both sides of a semiconductor wafer.

Fabrication of integrated circuits on both sides of a semiconductor wafer

A semiconductor device having shallow trench isolation (STI) is formed without dishing of the insulating material filling the trench, and without forming a planarization mask. Embodiments include forming a pad oxide layer and a polish stop layer, such as silicon nitride, on a semiconductor substrate, forming a trench in the substrate, and filling the trench with a first insulating layer, such as silicon dioxide. A second polish stop layer is then deposited on the first insulating layer, followed by a second, sacrificial insulating layer, such as silicon dioxide, to cover the second polish stop layer. The second insulating layer is then polished, as by CMP, to expose the second polish stop layer above the first polish stop layer, and the exposed portion of the second polish stop layer is then removed, as by wet etching, to expose the first insulating layer. The first and second insulating layers are then polished, as by CMP, to expose the first polish stop layer and the remaining portion of the second polish stop layer above the trench. The trench fill is planar at the trench edges and slightly higher than the main surface of the substrate, and exhibits no dishing. Thus, dishing of the trench fill is avoided without forming an expensive and complex planarization mask.

Shallow trench isolation formation without planarization mask

Channel doping and gate lithography are simulatneously performed by focusing an ion beam into the wafer through a positive or negative photoresist that is sensitive to the ion beam. Additional fabrication is then performed to provide a gate that is self-aligned with the doped channel.

Fully self-aligned high speed low power MOSFET fabrication

To attenuate a CMP polishing rate differential which tends to occur over the surface of a semiconductor substrate surface which has had one or more layers formed thereon, surface characteristics of the upper surface which are representative of the thickness, for example, of a layer which is being removed either in part or in its entirety, are monitored and surface profile information is developed using a suitable algorithm and used to control the timing with which force is applied by one or more of a plurality of actuators disposed on the other side of the wafer, in a manner wherein areas which have undergone more removal than others, are forced into contact with the polishing pad with a force which is reduced as compared that which is applied to localized high areas wherein a lesser amount of the layer has been removed.

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Sunnyvale, CA, United States of America

Weizhong Wang