Hewlett-packard Development Company, L.p.

Sun Microsystems, Inc.

Hewlett-packard Development, L.p.

Apache Design Solutions, Inc.

Weize Xie

Norman H Chang

Shen Lin

Osamu Samuel Nakagawa

Keunmyung Lee

Eileen H You

Richard M Chou

John F MacDonald

Yu Cao

Xuejue Huang

Kenynmyung Lee

An efficient inductance modeling approach for on-chip power-ground wires using their effective self-loop-inductances is disclosed. Instead of extracting the inductive coupling between every two parallel wires and putting this huge number inductance elements into circuit simulation, this technique determines the effective self-loop-inductance for each power or ground wire segment and only generates a circuit with these effective self-inductors for simulation. This approach greatly reduces the circuit size and makes the full-chip power-ground simulation with the consideration of inductance feasible.

On-chip power-ground inductance modeling using effective self-loop-inductance

A system and method to reduce leakage power consumption of electronic devices. In addition to assigning threshold voltages, sizes of the transistors within the device may be varied to provide a range of options to meet the timing requirements while minimizing the leakage power consumption.

System and method to reduce leakage power in an electronic device

A method determines a plurality of clock delay values. Each delay value is associated with a delay element on a clock line leading to a clock sink in a synchronous circuit. The method determines an initial set of delay values and executes an optimization algorithm, beginning with the initial set of delay values, to arrive at a set of delay values that at least approximately meets an criteria while satisfying timing constraints associated with selected pairs of logically connected clock sinks. In a preferred form, the optimization algorithm is a genetic algorithm or a gradient descent algorithm. The genetic algorithm involves selecting parent sets of delay values, crossing over so as to produce a child set of delay values, mutating the child set of delay values, evaluating how well the child set of delay values meets the criteria, and conditionally discarding the child set on the basis of the evaluating step. The gradient descent algorithm involves perturbing the initial set of delay values, evaluating how well the perturbed set of delay values meets the criteria, and conditionally discarding the perturbed set on the basis of the evaluating step. If the perturbed set is not discarded, then the gradient descent algorithm adjusts the values of the perturbed set in the same direction relative to the corresponding values in the initial set.

System and method for determining a plurality of clock delay values using an optimization algorithm

A method reduces noise resulting from a current surge in a circuit. A plurality of loading elements, parallel with the circuit being protected, are connected sequentially and disconnected. The connection of the loading elements results in a ramping up of current through the circuit without a sudden surge. In a preferred embodiment, an apparatus for slowing a current change in a circuit is described. The apparatus comprises a plurality of loading elements placed in parallel with the circuit, each of the elements providing a path for current flow, and a control circuit for selectively opening or closing at least one of said paths to prevent or enable current flow through the at least one of the paths.

Method for reducing current surge using multi-stage ramp shunting

A logic gate circuit and related methods and apparatus exhibit reduced voltage swing and thereby consume less power. The circuit is connected to a plurality of input signals and a clock signal. The circuit produces an output. The circuit comprises a node, a pull-down network and an N-type MOS transistor. The pull-down network is connected to the node, a first reference voltage, the plurality of inputs and the clock signal. The N-type MOS transistor is connected between the node and a second reference voltage. The N-type MOS transistor is also connected to a complement of the clock signal. A method of the invention accepts a complement of a clock signal and pre-charges a node to a voltage less than a power supply voltage, in response to the complement of the clock signal. The method also accepts a plurality of input signals and accepts the clock signal. The method conditionally discharges the node, in response to the clock signal, on the basis of the plurality of input signals.

Partial swing low power CMOS logic circuits

A system and method is provided for controlling clock skew to meet timing constraints for a semiconductor integrated circuit. On-chip self-tuning circuits can be connected to each latch in the integrated circuit for controlling clock skew. Each self-tuning circuit delays a clock signal that is input to a latch when the clock skew does not satisfy the timing constraint for that latch. The self-tuning circuit repeatedly delays the clock signal until the clock skew is satisfied or until the delay becomes greater than or equal to a predetermined threshold. The delayed clock signal is then pushed to other latches in the integrated circuit until all the timing constraints for the integrated circuit are satisfied.

Parallel push algorithm detecting constraints to minimize clock skew

An RLC module is configured to provide a simplified circuit modeling of a selected circuit net (or portion) of an electronic circuit. The RLC module may be configured to substitute an RLC circuit model for the selected circuit net, where the effective values of the capacitance and inductance for the RLC circuit model are retrieved from a table of capacitance and inductance values. A set of interconnect geometry factors (e.g., line length, line width, driver/receiver length, etc.) that describes the circuit net is used as an index into the table of capacitance and inductance values. The retrieved values of the effective capacitance and inductances values may be used to calculate a delay for the RLC circuit model. The RLC module may provide the capability to quickly calculate a delay for a selected circuit net without using computationally intensive calculations for inductance and capacitance values of circuit nets.

System for improving circuit simulations by utilizing a simplified circuit model based on effective capacitance and inductance values

A technique measuring accuracy of parasitic capacitance extraction defines the error in an extracted total net parasitic capacitance intended for timing analysis as a sum of the errors in the extracted values of the individual capacitance elements, with the error for each element being influenced by a weight factor. Similarly, the technique defines an error in the extracted value of a crosstalk factor for the net of interest as a difference between the errors in the extracted values of the individual capacitance elements, with the error in each element being influenced by a weight factor. For signal timing and crosstalk analyses, the weight factors allow a designer to focus calibration of the extraction tool on the capacitive element having the highest weight factor.

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Cupertino, CA, United States of America

Weize Xie