Freescale Semiconductor,inc.

Nxp Usa, Inc.

Semiconductor Components Industries, LLC

Weize Chen

Patrice M Parris

Richard J De Souza

Hubert Martin Bode

Md M Hoque

Xin Lin

Mark Griswold

John M McKenna

Andreas Laudenbach

Jaroslav Pjencak

Kurt U Neugebauer

Johan Camiel Julia Janssens

Moaniss Zitouni

Moshe Agam

Raymond Mervin Roop

Thierry Yao

Jennifer H Morrison

Jose Fernandez Villasenor

David E Niewolny

Mazhar Ul Hoque

Richard J DeSouza

Sameer S Haddad

Cheong Min Hong

Jane A Yater

Konstantin V Loiko

Bruce Greenwood

Kenneth Andrew Bates

In one embodiment, a transistor has a drift region that is formed to have a plurality of zones having different vertical doping profiles across the zones. At least one of the zones has a vertical doping profile that has a first peak near a top surface of the zone and a second peak near a bottom surface. An embodiment may have a lower doping in a region that is between the two peaks.

Semiconductor device

An embodiment of a semiconductor device may include a transistor having a first doped region and a second doped region that extend laterally underlying the source, body, and drain of the transistor. The transistor may have an embodiment that includes an additional bias contact to apply a bias potential to the first doped region and or alternately the second doped region.

An electronic device can include a NVM cell. The NVM cell can include a drain/source region, a source/drain region, a floating gate electrode, a control gate electrode, and a select gate electrode. The NVM cell can be fabricated using a process flow that also forms a power transistor, high-voltage transistors, and low-voltage transistors on the same die. A relatively small size for the NVM can be formed using a hard mask to define a gate stack and spacer between gate stack and select gate electrode. A gate dielectric layer can be used for the select gate electrode and transistors in a low-voltage region and allows for a fast read access time.

Process of forming an electronic device including a non-volatile memory cell

An electronic device can include a JFET that can include a drain contact region, a channel region spaced apart from the drain contact region, and a gate region adjacent the channel region. In an embodiment, the gate region includes a relatively heavier doped portion and a relatively lighter portion closer to the drain contact region. In another embodiment, a gate field electrode can be extended beyond a field isolation structure and overlie a channel of the JFET. In a further embodiment, a region having relatively low dopant concentration can be along the drain side of the conduction path, where the region is between two other more heavily doped regions. In another embodiment, alternating conducting channel and gate regions can be used to allow lateral and vertical pinching off of the conducting channel regions.

Electronic device including a junction field-effect transistor

A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.

Isolation structure for semiconductor device having self-biasing buried layer and method therefor

A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.

Semiconductor device with non-isolated power transistor with integrated diode protection

A method of forming a semiconductor device using a substrate includes forming a first select gate over the substrate, a charge storage layer over the first select gate, over the second select gate, and over the substrate in a region between the first select gate and the second select gate, wherein the charge storage layer is conformal, and a control gate layer over the charge storage layer, wherein the control gate layer is conformal. The method further includes performing a first implant that penetrates through the control gate layer in a middle portion of the region between the first select gate and the second select gate to the substrate to form a doped region in the substrate in a first portion of the region between the first select gate and the second select gate that does not reach the first select gate and does not reach the second select gate.

Split gate device with doped region and method therefor

Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.

Integrated circuits devices with counter-doped conductive gates

An embodiment of an Ion Sensitive Field Effect Transistor (ISFET) structure includes a substrate, source and drain regions formed within the substrate and spatially separated by a channel region, a gate dielectric and a gate formed over the channel region, multiple conductive structures overlying the surface of the substrate, and one or more protection diode circuits coupled between one or more of the multiple conductive structures and the substrate. The multiple conductive structures include a floating gate structure and a sense plate structure. The floating gate structure is formed over the gate dielectric and includes the gate. The sense plate structure is electrically coupled to the floating gate structure and is configured to sense a concentration of a target ion or molecule in a fluid adjacent to a portion of the sense plate structure.

Ion sensitive field effect transistors with protection diodes and methods of their fabrication

An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.

Methods and apparatus for an ISFET

A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed.

Method of fabricating a tunable schottky diode with depleted conduction path

Protected sensor field effect transistors (SFETs). The SFETs include a semiconductor substrate, a field effect transistor, and a sense electrode. The SFETs further include an analyte-receiving region that is supported by the semiconductor substrate, is in contact with the sense electrode, and is configured to receive an analyte fluid. The analyte-receiving region is at least partially enclosed. In some embodiments, the analyte-receiving region can be an enclosed analyte channel that extends between an analyte inlet and an analyte outlet. In these embodiments, the enclosed analyte channel extends such that the analyte inlet and the analyte outlet are spaced apart from the sense electrode. In some embodiments, the SFETs include a cover structure that at least partially encloses the analyte-receiving region and is formed from a cover material that is soluble within the analyte fluid. The methods include methods of manufacturing the SFETs.

Protected sensor field effect transistors

A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. At least one of the body region and the device isolating region includes a plurality of peripheral, constituent regions disposed along a lateral periphery of the active area, each peripheral, constituent region defining a non-uniform spacing between the device isolating region and the body region. The non-uniform spacing at a respective peripheral region of the plurality of peripheral, constituent regions establishes a first breakdown voltage lower than a second breakdown voltage in the conduction path.

Integrated breakdown protection

Semiconductor devices and related electrostatic discharge (ESD) protection methods are provided. An exemplary semiconductor device includes an interface for a signal and a multi-triggered protection arrangement coupled between the interface and a reference node to initiate discharge of the signal between the interface and the reference node based on any one of a plurality of different characteristics of the signal. Discharge of the signal at the interface is initiated based on a first characteristic of the signal, and thereafter, the discharge of the signal at the interface is maintained based on another characteristic of the signal.

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Phoenix, AZ, United States of America

Weize Chen