Texas Instruments Corporation

Weiyuen Kau

James J Walsh

Qadeer Ahmad Qureshi

Shannon A Wichman

John H Cornish

An electronic system ( ) includes a first integrated circuit (IC) ( ) having a card system management interrupt (SMI) output pin (CRDSMI&num;) and interrupt pins (IRQ ), and a logic circuit ( ) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate ( ) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate ( ) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN). A second integrated circuit ( ) has a system management interrupt (SMI&num;) output pin and SMI circuitry ( ) including a SMI register ( ) connected to events sources eligible for SMI response including the card SMI output of the first integrated circuit. This second IC ( ) further has a mask SMI register ( ) connected to the SMI register ( ) to select particular ones of the events sources for SMI response. A logic circuit ( ) is fed by the SMI register ( ) for combining the selected events sources to supply an internal SMI output (SMIOUT). Other circuits, systems and methods are also disclosed.

System management mode circuits, systems and methods

An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN). A second integrated circuit (110) has a system management interrupt (SMI#) output pin and SMI circuitry (2370) including a SMI register (2610) connected to events sources eligible for SMI response including the card SMI output of the first integrated circuit. This second IC (110) further has a mask SMI register (2620) connected to the SMI register (2610) to select particular ones of the events sources for SMI response. A logic circuit (2634, 2638) is fed by the SMI register (2610) for combining the selected events sources to supply an internal SMI output (SMIOUT). Other circuits, systems and methods are also disclosed.

Method and apparatus for handling system management interrupts (SMI) as

An electronic system (100) includes a register (TONTOFF) for data and a clock circuit (2340, 708) coupled to the register and responsive to the data in the register to generate a series of clock pulses (CPU.sub.-- CLK). The series of clock pulses occupies time intervals (2550) interspersed with time intervals free of clock pulses (2552), as an output having a ratio of the time intervals responsive to the data. Other devices, systems and methods are also disclosed.

Power management masked clock circuitry, systems and methods

An electronic system (6) has a power management logic circuit (920). A first power supply connector (1902) is electrically coupled to the power management logic circuit (920) and a second power supply connector (1904) is also electrically coupled to the power management logic circuit (920). The power management logic circuit (920) has a first logic section (920A) connected to the first power supply connector (1902), and the first logic section (920A) has a suspend output (SUSPEND#). A second logic section (920B) is connected to the second power supply connector (1904) for operation independent of the first logic section (920A) when power is available at the second power supply connector (1904, RTCPWR) and suspended at the first power supply connector (1902, VCC).

Power management interface system for use with an electronic wiring

A microcomputer integrated circuit (102) has a central processing unit (CPU) (702) first power management circuit (708) responsive to a system management interrupt (SMI) input for controlling operations of the CPU (702). A card interface integrated circuit (112) is adapted for coupling a card (24) to the microcomputer integrated circuit (102) and has a second power management circuit logic (1620, 1630) that responds to a plurality of interrupt event inputs (in CSC REGs A, B) and concentrates these inputs to a single card system management interrupt output (CRDSMI#). A peripheral processor integrated circuit (110) has a third power management circuit (920) including a plurality of system management interrupt (SMI) sources, and a SMI unit (2370). The SMI unit (2370) has an output (SMI#) connected to the SMI input of the microprocessor integrated circuit. The SMI unit (2370) responds to the card SMI output of the card interface integrated circuit (112) as well as the plurality of SMI sources. The plurality of SMI sources includes timer circuitry (2350) connected to power down terminals (IDEPWR#, FDDPWR#, SIUPWR#, PCSPWR#) for connection to external peripherals upon respective timeouts in the timer circuitry (2350). Other circuits, systems and methods are also described.

Computer system power management interconnection circuitry, systems and

Computer system power management interconnection circuitry, system and

An electronic system (6) has a power management logic circuit (920). A first power supply connector (1902) is electrically coupled to the power management logic circuit (920) and a second power supply connector (1904) is also electrically coupled to the power management logic circuit (920). The power management logic circuit (920) has a first logic section (920A) connected to the first power supply connector (1902), and the first logic section (920A) has a suspend output (SUSPEND#). A second logic section (920B) is connected to the second power supply connector (1904) for operation independent of the first logic section (920A) when power is available at the second power supply connector (1904, . . . RTCPWR) and suspended at the first power supply connector (1902, VCC). Other devices, systems and methods are also disclosed.

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Dallas, TX, United States of America

Weiyuen Kau