Nxp Usa, Inc.

Marvellworld Trade Ltd.

Marvell International Limited

Marvell Asia Pte., Ltd.

Weiwei Xu

Xiaoyue Wang

Yui Lin

Sai-Wang Tam

Alden C Wong

Sridhar Reddy Narravula

Jue Yu

Dipen Bakul Parikh

Yi-Ling Chao

Norman Liu

Prasanna Upadhyaya

Arvind Anumula Paramanandam

Alireza Razzaghi

Anuranjan Jha

One example discloses an analog to digital converter (ADC), including: an analog comparator configured to receive an analog input signal and in response generate a comparator output signal; a set of digital to analog converter (DAC) elements configured to receive the analog input signal; wherein the DAC elements are configured to generate an analog DAC output signal in response to a digital code and the analog input signal; wherein the comparator is configured to receive the analog DAC output signal; a feedback circuit configured to generate a first feedback signal and a second feedback signal from the comparator output signal; a controller configured to enable a first set of controller elements in response to the first feedback signal; wherein the controller configured to enable a second set of controller elements in response to the second feedback signal; and wherein the controller elements are configured to generate the digital code.

Multi-phase analog to digital converter (ADC)

Embodiments of a calibration system for third order intermodulation distortion (IMD3) cancellation and a wireless apparatus are disclosed. In an embodiment, a calibration system for IMD3 cancellation includes a cancellation circuit for IMD3 cancellation between a first transmitter and a second transmitter, and a controller coupled to the cancellation circuit and configured to for each frequency channel of the first transmitter, perform a pre-conditional calibration of the cancellation circuit, after the pre-conditional calibration, determine a phase configuration for the cancellation circuit, and after the phase configuration for the cancellation circuit is determined, determine an attenuation configuration for the cancellation circuit.

Pre-conditional calibration for third order intermodulation distortion (IMD3) cancellation

Embodiments of a differential bootstrapped track-and-hold circuit are disclosed. In an embodiment, the differential bootstrapped track-and-hold circuit includes first and second single-ended bootstrapped track-and-hold circuits. Each single-ended bootstrapped track-and-hold circuit includes a sampling switch connected between an input terminal and an output terminal, a sampling capacitor connected to the output terminal, and a dummy sampling switch connected between the input terminal and a dummy output terminal. The sampling switch and the dummy sampling switch are controlled by a bootstrap driver connected to the input terminal. The dummy output terminal of the first single-ended bootstrapped track-and-hold circuit is connected to the output terminal of the second single-ended bootstrapped track-and-hold circuit and the dummy output terminal of the second single-ended bootstrapped track-and-hold circuit is connected to the output terminal of the first single-ended bootstrapped track-and-hold circuit to provide signals to compensate for charge injection errors at the output terminals.

Differential bootstrapped track-and-hold circuit with cross-coupled dummy sampling switches

Various embodiments relate to a cancellation circuit configured to generate a cancellation signal, including: an attenuator configured to attenuate a transmitted signal from an aggressor transmitter based upon a first attenuation value; an I/Q demodulator configured to split an attenuated signal into in-phase (I) and quadrature signals (Q); a phase interpolator configured to apply a calibration phase shift and a calibration attenuation to the I signal and Q signal and to recombine the I and Q signals; an auxiliary balun coupled to an output of the phase interpolator; and an auxiliary power amplifier with an input connected to the auxiliary balun configured to generate the cancellation signal, wherein the output of the auxiliary power amplifier is connected to an output of a victim transmitter.

Third order intermodulation distortion cancellation

A reconfigurable regulator includes an error amplifier configured to generate a difference signal indicative of a voltage difference between a reference analog signal and a feedback analog signal; a pulse width modulation generator configured to receive the difference signal, and to generate a first pulse width modulated signal in a linear mode and a second pulse width modulated signal in a switching mode; and a digital multiplexer (MUX) configured to receive a mode selection signal, the first pulse width modulated signal and the second pulse width modulated signal. The digital MUX outputs one of the first pulse width modulated signal or the second pulse width modulated signal based on the mode selection signal. The reconfigurable regulator further includes a digital driver configured to receive one of the first pulse width modulated signal or the second pulse width modulated signal and to output a digital control signal based on the received one of the first pulse width modulated signal or the second pulse width modulated signal.

Reconfigurable regulator for regulating power in linear and switching modes

Embodiments described herein provide a voltage regulator that includes an error amplifier configured to provide a difference signal indicative of a voltage difference between a reference signal and a feedback signal, a pulse width modulation generator configured to receive the difference signal and to output a pulse width modulated signal based on the difference signal, and one or more transistors configured to receive the pulse width modulated signal at a gate of the one or more transistors, and to provide the feedback signal at a drain of the one or more transistors as a regulated voltage that is adjusted to match the reference signal so as to reduce the voltage difference between the reference signal and the feedback signal.

Class-D driven low-drop-output (LDO) regulator

A method includes providing a first voltage to a first output node during a first time interval, providing a second voltage to the first output node during a second time interval, and averaging the first and second voltages to provide a reference voltage to a second output node. The first voltage includes a proportional-to-absolute-temperature (PTAT) component, a complementary-to-absolute-temperature (CTAT) component, and a first residual offset component. The second voltage includes the PTAT component, the CTAT component, and a second residual offset component. An apparatus includes a discrete-time circuit to provide the first voltage to the first output node during the first time interval and to provide the second voltage to the first output node during the second time interval, and a filter to average the first and second voltages to provide the reference voltage to the second output node.

Switched-capacitor bandgap reference circuit using chopping technique

Systems and techniques relating to a digital-to-analog converter (DAC) are described. A described DAC cell includes a differential switch pair coupled with a cross-coupled switch pair. Gate terminals of the differential switch pair are arranged to respectively receive an input signal to the cell and an inverted version of the input signal to respectively drive the gate terminals of the differential switch pair. Gate terminals of the cross-coupled switch pair are arranged to respectively receive the input signal and the inverted version of the input signal to respectively drive the gate terminals of the cross-coupled switch pair. The cross-coupled switch pair is configured to reduce or eliminate net differential transient current between switch output terminals of the differential switch pair. A current-to-voltage converter coupled with the switch output terminals of the differential switch pair generates a voltage that forms at least a portion of an output of the digital-to-analog converter.

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San Jose, CA, United States of America

Weiwei Xu