Southeast University

Weiwei Shan

Longxing Shi

Jun Yang

Lixuan Zhu

Peng Cao

Yang Zhang

Xinning Liu

Tao Wang

Na Bai

Ziyu Li

Liang Wan

Haolin Gu

Xuexiang Wang

Tao Zhao

Chaoxuan Tian

Wentao Dai

Huafang Sun

The present invention discloses an ultralow-power negative margin timing monitoring method of a neural network circuit, relates to an adaptive voltage regulation technology based on on-chip timing detection, and belongs to the technical field of low-power design of integrated circuit. The present invention provides an ultralow-power operating method of neural network circuit. By inserting a timing monitoring unit in specific position of critical paths and setting partial circuits to operate under 'negative margin', the system can further lower voltage, compress the timing slack, and obtain higher power gain.

Ultra low-power negative margin timing monitoring method for neural network circuit

It discloses a serial FFT-based low-power MFCC speech feature extraction circuit, and belongs to the technical field of calculation, reckoning or counting. The circuit is oriented toward the field of intelligence, and is adapted to a hardware circuit design by optimizing an MFCC algorithm, and a serial FFT algorithm and an approximation operation on a multiplication are fully used, thereby greatly reducing a circuit area and power. The entire circuit includes a preprocessing module, a framing and windowing module, an FFT module, a Mel filtration module, and a logarithm and DCT module. The improved FFT algorithm uses a serial pipeline manner to process data, and a time of an audio frame is effectively utilized, thereby reducing a storage area and operation frequency of the circuit under the condition of meeting an output requirement.

Serial FFT-based low-power MFCC speech feature extraction circuit

It discloses a speech feature reuse-based storing and calculating compression method for a keyword-spotting CNN, and belongs to the technical filed of calculating, reckoning or counting. If the updated row number of input data is equal to a convolution step size, every time new input data arrive, an input layer of a neural network replaces the earliest part of the input data with the new input data and meanwhile adjusts an addressing sequence of the input data, thereby performing an operation on the input data and corresponding convolution kernels in an arrival sequence of the input data, and an operation result is stored in an intermediate data memory of the neural network to update corresponding data.

Speech feature reuse-based storing and calculating compression method for keyword-spotting CNN

The present invention discloses an ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial fast Fourier transform (FFT), and belongs to the technical field of computation, calculation or counting. The circuit is oriented to the field of intelligence, and is integrally composed of a pre-process module, a windowing module, a Fourier transform module, a Mel filtering module, an adjacent frame merging module, a discrete cosine transform (DCT) module and other modules by optimizing the architecture of a Mel-frequency Cepstral Coefficients (MFCC) algorithm. Large-scale storage caused by framing is avoided in a non-overlapping framing mode, storage contained in the MFCC algorithm is further reduced, and the circuit area and the power consumption are greatly reduced. An FFT algorithm in the feature extraction circuit adopts a serial pipeline mode to process data, makes full use of the characteristics of serial inflow of audio data, and further reduces the storage area and operations of the circuit.

Ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial FFT

An in-memory computing circuit for a fully connected binary neural network includes an input latch circuit, a counting addressing module, an address selector, a decoding and word line drive circuit, a memory array, a pre-charge circuit, a writing bit line drive circuit, a replica bit line column cell, a timing control circuit, a sensitive amplifier and a NAND gate array, an output latch circuit and an analog delay chain. A parallel XNOR operation is performed in the circuit on the SRAM bit line, and the accumulation operation, activation operation and other operations are performed by the delay chain in the time domain. Partial calculation is completed while reading the data, and the delay chain with a small area occupation can be integrated with SRAM, thus reducing the energy consumption of the memory access process. Multi-column parallel computing also improves system throughput.

In-memory computing circuit for fully connected binary neural network

A two-way adaptive clock circuit supporting a wide frequency range is composed of a phase clock generating module, a phase clock selecting module, an adaptive clock stretching or compressing amount regulating circuit module and a control module. The adaptive clock stretching or compressing amount regulating circuit module can monitor delay information of a critical path in a chip in real time and feed the information back into the control module. After receiving a clock stretching or compressing enable signal and a stretching or compressing scale signal, the control module selects a target phase clock from clocks generated by the phase clock generating module to rapidly regulate an adaptive clock in a current cycle. The present invention is applied to an adaptive voltage frequency regulating circuit based on on-line time sequence monitoring.

Bi-directional adaptive clocking circuit supporting a wide frequency range

A process corner detection circuit based on a self-timing ring oscillator comprises a reset circuit (), the self-timing oscillation ring (), and a counting module (). The self-timing ring oscillator () consists of m two-input Muller C-elements and inverters, and a two-input AND gate, m being a positive integer greater than or equal to 3. The circuit can be used for detecting a process corner of a fabricated integrated circuit chip, and reflecting the process corner of the chip according to the number of oscillations of the self-timing ring oscillator (). The number of oscillations of the self-timing ring oscillator () in different process corners is acquired by Hspice simulation before the chip tape-out, and the process corner of the chip after the chip tape-out can be determined according to the actually measured number of oscillations.

Process corner detection circuit based on self-timing oscillation ring

An online monitoring unit and a control circuit for ultra-wide voltage range applications are disclosed. Compared with a conventional online monitoring unit, present invention eliminates a need to reserve delay units, replaces flip-flops in the conventional online monitoring unit with a latch, and uses a transition detector with fewer transistors than that of a shadow latch in the conventional online monitoring unit, thereby reducing an area and a power consumption of the online monitoring unit significantly and improving an energy efficiency of online monitoring techniques. In addition, in the ultra-wide voltage range applications, a time borrowing property of the latch adopted by the present invention can be utilized to prevent a timing error caused by process-voltage-temperature (PVT) variations, thus enabling a minimization of a timing margin and ensuring a higher power efficiency. The present invention also discloses a control circuit for use with the online monitoring unit.

Online monitoring unit and control circuit for ultra-wide voltage range applications

A PVTM-based wide voltage range clock stretching circuit is disclosed. The circuit consists of a PVTM circuit module, a phase clock generation module, a clock synchronization selection module and a control module. The PVTM circuit module monitors in real time the delay information of an on-chip delay unit to monitor the operating environment of the circuit, and feeds the delay information back to the control module. Under the control of a clock stretching enable signal and a clock stretching extent signal, the control module selects a target phase clock from the clocks generated by the phase clock generation module in accordance with the feedback from the PVTM, enabling the stretching of system clock within a single cycle in different PVT conditions. Sophisticated gate devices are not required, and the cost of area and power consumption are kept to minimal.

PVTM-based wide voltage range clock stretching circuit

Disclosed is an error recovery circuit facing a CPU assembly line, comprising: on-chip monitoring circuits (), an error signal statistics module (), a voltage frequency control module (), an error recovery control module (), an in-situ error recovery module () and an upper-layer error recovery module (), wherein each of the on-chip monitoring circuits () is integrated at the end of each stage of assembly lines of the previous N&#x2212;1 stages of assembly lines of a CPU kernel with an N-stage assembly line structure, so as to monitor the time sequence information about each clock period of an operating circuit, wherein N is a positive integer which is greater than or equal to 3 and less than 20. The present invention provides the on-line time sequence monitoring on the CPU kernel with N stages of assembly lines to search for the lowest possible operating voltage of the circuit, and to reduce the margin of the operating voltage reserved for the circuit in the design stage, thereby significantly reducing the power consumption of the circuit and improving the energy efficiency of the circuit.

Error recovery circuit oriented to CPU pipeline

A dynamic voltage scaling system based on on-chip monitoring and voltage prediction is disclosed, comprising a main circuit that has integrated on-chip monitoring circuits, a supply voltage scaling module, and voltage converters, wherein, the supply voltage scaling module comprises a sampling and statistics module designed to calculate the error rate of the main circuit in the current time slice, a state recording module designed to record the error rate and the corresponding supply voltage, an error prediction module, and a state transition probability generation module; the error prediction module predicts the error trend of the main circuit in a future time slice according to the state recording module and the state transition probability generation module, and generates regulation signals and sends to the corresponding voltage converters, so as to generate the voltage required for operation of the entire main circuit.

Dynamic voltage scaling system based on on-chip monitoring and voltage prediction

The present invention discloses a Power-On-Reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage. The POR circuit achieves zero steady-state current consumption during steady operation after the POR process by cutting off a power supply to a band-gap comparator circuit and a current comparator circuit after the POR process. The present invention has high reliability and stable pull-up voltage, is less susceptible to the impact of power-on rate of power supply, temperature, and process variation, has very low steady-state power consumption, and can be integrated in a SOC chip in low-power consumption applications.

Growing community of inventors

Nanjing, China

Weiwei Shan