Agere Systems Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Lsi Corporation

Weiwei Mao

Mohammad Shafiul Mobin

Brett D Hardy

Christopher John Abel

Ye Liu

Lane Allen Smith

William Burdett Wilson

Freeman Yingquan Zhong

Xingdong Dai

Max Jay Olsen

Kenneth Wade Paist

Shahriar Moinian

Geoffrey Zhang

Mingdeng Chen

Chintan M Desai

Andrew Cable

Ari Valero-Lopez

An apparatus for powering an electrical circuit includes a first voltage input configured to receive power from a first voltage source, a second voltage input configured to receive power from a second voltage source, wherein the second voltage source has a lower voltage than the first voltage source, a voltage regulator connected to the first voltage input, and a voltage output configured to switchably receive power from the first voltage input through the voltage regulator or from the second voltage input.

Transmitter power supply with selective source and regulation

Described embodiments provide for, in a SerDes device, an adaptation process that adjusts data path gain through programmable-bias based on process, voltage, temperature (PVT) and data rate changes. Such adaptation process extends bias current dynamic range, and low frequency gain can be programmed to a desired target range of values for a given variable gain amplifier (VGA) setting at any PVT and data rate corner. A receive (RX) data path structure auto-adapts data path gain through programmable bias based on sensed PVT and data rate changes. The low frequency attenuation/gain range is extended, and can be programmed to a desirable targeted range by a SerDes device RX adaptive process for a given VGA and linear equalizer (LEQ) setting at any given PVT and data rate condition.

Data rate and PVT adaptation with programmable bias control in a SerDes receiver

In described embodiments, process, voltage, temperature (PVT) compensation in a serializer/deserializer (SerDes) device employs a closed loop adaptation compensation that is incorporated into the SerDes receiver adaptation process. A detection method, where the adapted decision feedback equalizer (DFE) target level (e.g., tap H) is monitored, employs this DFE target level when implementing a closed loop variable gain amplifier adaptation. The DFE target level in conjunction with the VGA level is used to control the PVT setting to maintain target SerDes data path gain by detecting aPVT corner condition. The detected PVT corner condition is employed to generate a control signal to further adjust the LEQ and DFE data path differential pair gain as required by the PVT condition.

SerDes PVT detection and closed loop adaptation

A tap coefficient control circuit and a method for controlling a tap coefficient for a decision feedback equalizer are disclosed. The method includes adjusting a correction voltage applied to the tap coefficient based on a first tap quantization and detecting a decision feedback equalizer tap convergence. After the decision feedback equalizer tap convergence is detected, the method adjusts the correction voltage applied to the tap coefficient based on a second tap quantization, wherein the second tap quantization is different from the first tap quantization.

Pre and post-acquisition tap quantization adjustment in decision feedback equalizer

An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.

Integrated circuit inductors with reduced magnetic coupling

A method and system for modeling and calibrating duty cycle distortion (DCD) of a Serializer and Deserializer (SerDes) device, including first generating a clock DCD signal. Once the clock DCD signal is generated, it is calibrating based upon results obtained from a filtering process of the clock DCD signal. Once the clock DCD signal is calibrated, a data DCD signal is generated and calibrated based upon results obtained from a filtering process of the data DCD signal.

Duty cycle distortion (DCD) jitter modeling, calibration and generation methods

Various embodiments of the present invention provide systems and circuits that provide for out of band detection. As one example, an out of band detection circuit is disclosed that includes an input signal, a clock generation circuit, and a sampling circuit. The clock generation circuit receives the input signal and derives therefrom a sampling clock, and the sampling circuit is operable to sample the input signal at a time indicated by the sampling clock.

Systems and methods for determining an out of band signal

Methods and apparatus are provided for controlling at least one of a rise time and a fall time of a signal. A plurality of time shifted clock signals are generated; and a received data signal is sampled using a plurality of parallel data paths, where each of the data paths are controlled by a corresponding one of the plurality of time shifted clock signals. The plurality of time shifted clock signals can be generated, for example, by at least one delay element. The plurality of parallel data paths can be substantially identical and comprise, for example, at least one latch or at least one flip flop. Compensation can optionally be provided for variations in, for example, process corner, supply voltage, aging and operating temperature.

Method and apparatus for slew rate control

A buffer for interfacing complementary input signals having first logical voltage levels to a circuit operating with second logical voltage levels includes first and second branches outputting first and second complementary output signals, respectively. Each branch includes a PMOS and an NMOS transistor connected in series with a voltage-swing adjusting transistor between a first supply voltage and a second supply voltage. Control terminals of the PMOS and NMOS transistors each receive one of the complementary input signals, and a control terminal of the first voltage-swing adjusting transistor receives a first bias voltage. When the complementary input signal has a first voltage level, the voltage-swing adjusting transistor operates in a linear region and when the first complementary input signal has a second voltage level, current through the voltage-swing adjusting transistor is shut-off. No current flows in either branch when the buffer is in a static state.

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Macungie, PA, United States of America

Weiwei Mao