Ningbo University

Weiwei Chen

Pengjun Wang

Yuejun Zhang

Qian Wang

Daohui Gong

Yan Li

Keji Zhou

Dong Zhang

Haoyu Qian

Yuefeng Wang

A mid-infrared gas sensor based on a tapered sub-wavelength grating slot waveguide comprises a lower cladding, a first tapered grating array and a second tapered grating array. The first tapered grating array and the second tapered grating array are disposed on an upper surface of the lower cladding. The first tapered grating array is located in front of the second tapered grating array. The first tapered grating array is formed by 5566 identical first core waveguides that are regularly distributed at intervals from left to right. The second tapered grating array is formed by 5566 identical second core waveguides that are regularly distributed at intervals from left to right. The first core waveguides and the second core waveguides are tapered waveguides. Upper sides and lower sides of the first core waveguides and the second core waveguides are isosceles trapezoids.

Mid-infrared gas sensor based on tapered sub-wavelength grating slot waveguide

The present invention discloses a CNFET double-edge pulse JKL flip-flop, comprising a double-edge pulse signal generator, 31 CNFET tubes, 6 NTI gate circuits having the same circuit structure, 6 PTI gate circuits having the same circuit structure as well as the 1and 2two-value inverters having the same circuit structure; it features in correct logic functions as well as high-speed and low power consumption.

CNFET double-edge pulse JKL flip-flop

The present invention discloses a static RAM for defensive differential power consumption analysis, comprising a replica bit-line circuit, a decoder, an address latch circuit, a clock circuit, n-bit memory arrays, n-bit data selectors, n-bit input circuit and n-bit output circuits; the output circuits comprises a sensitivity amplifier and a data latch circuit; the 1st PMOS tube, the 2nd PMOS tube, the 3rd PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the 1st NMOS tube, the 2nd NMOS tube, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube constitute the sensitivity amplifier; two NOR gates, the 8th PMOS tube, the 9th PMOS tube, the 10th PMOS tube, the 11th PMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube and the 10th NMOS tube constitute the data latch circuit; the present invention is characterized in that energy consumption in each working cycle is basically identical, which is provided with higher capability in defense of differential power analysis.

Static RAM for differential power analysis resistance

The present invention discloses a bridge imbalance PUF unit circuit and multi PUF circuits; the bridge imbalance PUF unit circuit comprises a four-arm bridge unit circuit and a contrast output unit circuit; the multi PUF circuits comprise a timing controller, a row decoder, a column decoder, a memory array, a row output circuit and a column output circuit; each memory unit in the memory array comprises a bridge imbalance PUF unit circuit and 4 NMOS tubes; the present invention features in higher randomness that is up to 51.8% at the supply voltage of 1.2V under the temperature of 25&#xb0; C.

Growing community of inventors

Zhejiang, China

Weiwei Chen