Macronix International Co., Ltd.

Weitong Chuang

Chun-Hsiung Hung

Kuen-Long Chang

Ray-Lin Wan

Tzeng-Huei Shiau

Yin-Shang Liu

Fuchia Shone

Han Sung Chen

Yao-Wu Cheng

Yuan-Chang Liu

Yu-Sui Lee

Kong Mou Liou

The present invention discloses a regulator system (,) for regulating the output current and voltage (Vout) of a charge pump circuit (,). It is observed that the output current and voltage (Vout) of a charge pump circuit (,) can be regulated by varying the amplitude and frequency of a set of clock signals (modulated clocks). The present invention comprises means (decoders,AM, FM units) for generating a set of control signals (VAD,-VFDn) as the function of the output current and voltage (Vout). The set of control signals (VAD,-VFDn) is coupled to a clock signal generation circuit (,) that generates a set of clock signals (modulated clocks) having a magnitude and a frequency depending on this set of at least one control signal. This set of clock signals (modulated clocks) is then used to drive the charge pump circuit (,). It is found that this regulator circuit (,) consumes less power than prior art regulator circuits.

Regulator system for charge pump circuits

Write protected, non-volatile memory device with user programmable

On chip voltage generation for low power integrated circuits

The present invention provides a new (ATD) address transition detection circuit for use on an address bus having any number of address lines. An ATD circuit is disclosed which comprises a first and second circuit and an interval timer. The first circuit has a first and second input and an output. The first circuit receives, at the first input, a change signal corresponding to transitions in one or more addresses of an address bus. In response, the output of the first circuit transitions from an initial first state to a second state. The first circuit is also responsive to a reset command at the second input to return the output to the first state. The interval timer has an output coupled to the second input of the first circuit and an input. The interval timer responsive to an initialize command at the input initiates a timed interval and after the timed interval generates the reset command at the output. The second circuit has an output coupled to the input of the interval timer and an input. The second circuit responsive to the change signal at the input generates an initialize command at the output. The circuit provides a second state at the output of the first circuit, for all including the last received in a series of change signals. This assures that all address transitions have been detected before a memory access is allowed.

Address transition detection circuit for a semiconductor memory capable

Flash memory device with multiple checkpoint erase suspend logic

Flash memory erase with controlled band-to-band tunneling current

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Taichung, Taiwan

Weitong Chuang