Xilinx, Inc.

Weirong Jiang

Gordon John Brebner

Mark Brian Carson

Yi-Hua Edward Yang

Denis Rystsov

Mark B Carson

In an example, an integrated circuit (IC) includes a memory including at least one random access memory (RAM). Each of the at least one RAM stores bits representing match vectors indicative of whether search keys match ternary rules. The IC further includes a verification circuit, coupled to the memory, operable to verify the bits stored in the at least one RAM by performing at least one of: decoding at least one of the ternary rules from the bits stored in the at least one RAM; or checking the bits stored in the at least one RAM against expected content of at least one of the ternary rules.

Verification of a RAM-based TCAM

Circuits and methods are disclosed for decomposition of a content addressable memory into a plurality of CAMs having a lower cost. In an example implementation, a set of CAM rules are grouped into a plurality of subsets. For each of the subsets, CAM rules in the subset are reformatted for storage in a respective CAM configured to store fewer ternary bits or configured for prefix match. Each reformatted subset of CAM rules are stored in the respective CAM. A search key formatting circuit is configured to reformat an input search key for each of the respective CAMs is used to store the reformatted subsets to produce a respective reformatted search key and input the respective reformatted search key to the respective CAM.

Content addressable memory decomposition

A system for processing data includes a filtering module having a plurality of processing units, a state accumulator, and a merging network coupled to the processing units and the state accumulator. Each processing unit is configured to output a set of two sub-state vectors and a packet continuance indicator. The state accumulator is configured to store a state resulted from previous processing cycles by the processing units. The merging network is configured to output a master state vector based at least in part on the set of two sub-state vectors, the stored state, and the packet continuance indicators output from the processing units.

High throughput packet state processing

Methods and apparatus for using dynamic programming to determine the most efficient mapping of a pipeline of virtual flow tables (VFTs) onto a pipeline of physical flow tables (PFTs) in the data plane of a software-defined networking (SDN) device are described. One example method of determining a configuration for an SDN device generally includes receiving a representation of a series of one or more VFTs, each of the VFTs having one or more properties; receiving a representation of a series of one or more PFTs for hardware of the SDN device, each of the PFTs having one or more capabilities; generating, using dynamic programming based on the properties of the VFTs and the capabilities of the PFTs, a mapping of the series of VFTs onto the series of PFTs; and outputting the generated mapping for implementation on the hardware of the SDN device.

Efficient mapping of table pipelines for software-defined networking (SDN) data plane

Devices and methods for performing a cyclic redundancy check are disclosed. For example, a device has a splitter for splitting a data word into a plurality of paths. The device also has a plurality of cyclic redundancy check units. Each of the units is for processing a respective one of the paths. In addition, each of the units includes a first output port for outputting a cyclic redundancy check value for a packet ending within the unit and a second output port for outputting a cyclic redundancy check value for a packet starting or ongoing within the unit.

Modular and scalable cyclic redundancy check computation circuit

In an FSM circuit, look-ahead-cascade modules are coupled to receive possible states and corresponding subsets of data inputs. Merge modules are coupled to a second-to-the-lowest to highest order of the look-ahead-cascade modules. The second-to-the-lowest to highest order of disambiguation modules are coupled to at least a portion of the merge modules. The lowest order of the disambiguation modules is coupled to the lowest order of the look-ahead-cascade modules. The lowest-to-highest order of the disambiguation modules are coupled to receive respective sets of interim states of rN states each to select respective sets of next states of r states each. A state register is coupled to receive a portion of the highest order of the sets of next states to provide a select signal. Each of the disambiguation modules is coupled to receive the select signal for selection of the sets of next states of the r states each.

High throughput finite state machine

A memory is disclosed that includes one or more TCAM memory units, each configured to store a respective set of rules. Each unit has an input coupled to receive an input search key from an input of the memory and includes a plurality of stages 1 through H. Each stage is configured to receive a respective multi-bit segment of the input search key and provide a result segment in response thereto. The result segment includes, for each rule of the respective set of rules, a bit that indicates whether or not the rule matches the segment of the input search key. Each unit also includes a first output circuit configured to generate a combined result indicating which rules match all of the respective segments received by each of the plurality of stages. The memory can also include one or more update circuits to update rules in a plurality of units.

Growing community of inventors

San Jose, CA, United States of America

Weirong Jiang