Lsi Logic Corporation

Sun Microsystems, Inc.

Integrated Silicon Solution Incorporated

Oregon Graduate Institute of Science & Technology

Weiran Kong

Yauh-Ching Liu

Helmut Puchner

Ruggero Castagnetti

Gary K Giust

Franklin Duan

Steven Michael Peterson

Sudhakar Bobba

Ramnath Venkatraman

David J Greenhill

Rajendra Solanki

Shafqat Ahmed

Myron J Buer

Bernard Ho

Minh Tien Nguyen

Lee Phan

Kai-Ning Chang

A capacitor structure in a semiconductor device is provided. The capacitor structure includes a first power rail on a topmost level of the semiconductor device, and a second power rail on the topmost level of the semiconductor device. The capacitor structure also includes a dielectric layer disposed over at least a portion of one of the first power rail and the second power rail. The capacitor structure further includes a conductive layer disposed over and between the first power rail and the second power rail where the conductive layer is in electrical contact with the power rail not having the dielectric layer, and the conductive layer is disposed over the dielectric layer.

Thin capacitive structure

An integrated circuit structures such as an SRAM construction wherein the soft error rate is reduced comprises an integrated circuit structure formed in a semiconductor substrate, wherein at least one N channel transistor is built in a P well adjacent to one or more deep N wells connected to the high voltage supply and the deep N wells extend from the surface of the substrate down into the substrate to a depth at least equal to that depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell. For a 0.25 &mgr;m SRAM design having one or more N wells of a conventional depth not exceeding about 0.5 &mgr;m, the depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell is from 1 to 3 &mgr;m. The deep N well of the 0.25 &mgr;m SRAM design, therefore, extends down from the substrate surface a distance of at least about 1 &mgr;m, and preferably at least about 2 &mgr;m. In a preferred embodiment, the implantation of the substrate to form the deep N well of the improved SRAM of the invention is carried out in a manner which will cause straggle, i.e., cause the doped volume comprising the deep N well to broaden at its base. Such a broadened base deep N well will have enhanced opportunity to collect electrons generated by the alpha particle collision with the substrate. This deep N well with a broadened base can be formed either by increasing the implant energy or by tilting the substrate with respect to the axis of the implant beam while implanting the substrate to form the deep N well.

Reduced soft error rate (SER) construction for integrated circuit structures

A method for fabricating an SRAM device having a standard well tub, where an additional well tub is deposited within the standard well tub. In this manner, the dopant concentration is increased in the well area of the SRAM device, which increases both the isolation punchthrough tolerance and the SER immunity of the device. The additional well tub is deposited to a depth that is shallower than the standard well tub. The additional well tub is deposited using an ion implantation process using the same mask set as that used for the threshold voltage adjustment deposition. Thus, no additional mask layer is required to deposit the additional well tub, and the all of the expenses normally associated with an additional mask layer are avoided.

System to improve ser immunity and punchthrough

A method of forming a memory cell according to the present invention. A first pass gate transistor is formed of a first transistor type. The first pass gate transistor has a gate oxide with a first thickness. The source of the first pass gate transistor is electrically connected to a first bit line, and the drain of the first pass gate transistor is electrically connected to a first state node. The gate of the first pass gate transistor is electrically connected to a memory cell enable line. A second pass gate transistor is also formed of the first transistor type. The second pass gate transistor also has a gate oxide with the first thickness. The source of the second pass gate transistor is electrically connected to a second bit line, and the drain of the second pass gate transistor is electrically connected to a second state node. The gate of the second pass gate transistor is electrically connected to the memory cell enable line. A first state node transistor is also formed of the first transistor type. The first state node transistor has a gate oxide with a second thickness. The source of the first state node transistor is electrically connected to the first state node, and the drain of the first state node transistor is electrically connected to a ground line. The gate of the first state node is electrically connected to the second state node. A second state node transistor is also formed of the first transistor type. The second state node transistor also has a gate oxide with the second thickness. The source of the second state node transistor is electrically connected to the second state node, and the drain of the second state node transistor is electrically connected to the ground line. The gate of the second state node is electrically connected to the first state node.

Single channel four transistor SRAM

A method for reducing stray conductive material near vertical surfaces in semiconductor manufacturing processes comprising the following steps. Deposit the gate oxide, polysilicon and cap oxide layers. Apply a Poly1A mask. The Poly1A mask pattern comprises the Poly1 areas that are part of the final circuit layout as well as additional Poly1 areas that are included to provide planar surfaces to prevent stringer formation. Etch the cap, polysilicon and gate oxide layers to partially form the transistor gate structures. Form oxide spacers on the sides of the transistor gate structures. Apply a source/drain mask. Deposit source/drain dopants to form diffusions. Deposit an interlayer dielectric. Mask and pattern contacts to the diffusions and the Poly1 layer. Deposit blanket TiN/Ti layer(s). Pattern the TiN/Ti layer(s) using a TiN/Ti mask and a dry anisotropic etch. Patterning the TiN/Ti layer(s) may create TiN/Ti stringers along vertical surfaces of the interconnect layer. However, by defining the Poly1A mask pattern to leave Poly1 in pre-defined potential stringer problem areas, these surfaces remain planar and thus free of stringers. Next, apply a Poly1B mask. The Polyl1B mask is defined such that the final Poly1 pattern is the logical AND of the Poly1A mask pattern and the inverse of the Poly1B mask. Then etch the cap, polysilicon and gate oxide layers to complete formation of the transistor gate structures.

Method for reducing stray conductive material near vertical surfaces in

A bright, short wavelength blue-violet phosphor for electroluminescent displays comprises an alkaline-based halide as a host material and a rare earth as a dopant. The host alkaline chloride can be chosen from the group II alkaline elements, particularly strontium chloride (SrCl.sub.2) or calcium chloride (CaCl.sub.2), which, with a europium (Eu) or cerium (Ce) rare earth dopant, electroluminesces at a peak wavelength of 404 and 367 nanometers (nm) respectively. The resulting emissions have CIE chromaticity coordinates which lie at the boundary of the visible range for the human eye thereby allowing a greater range of colors for full color flat panel electroluminescent (FPEL) displays.

Blue-violet phosphor for use in electroluminescent flat panel displays

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Sunnyvale, CA, United States of America

Weiran Kong