Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Grace Semiconductor Manufacturing Corporation

Weiran Kong

Jian Hu

Jing Gu

Bo Zhang

Jun Xiao

Hong Jiang

Binghan Li

Yi Xu

Bin Zhang

Guangjun Yang

Hualun Chen

An SAR ADC and a conversion method, which include an SAR control logic circuit configured to control A/D conversion by: 1) sampling analog input signal for first time; 2) subjecting the sampled signal to conversions; 3) sampling analog input signal for another time; 4) subjecting the sampled signal in step 3) to conversion including: i) determining whether the lowest M bits of previous N-bit digital output signal are 1's or 0's, if so, looping back to step 2), otherwise, proceeding to step ii); ii) performing conversions on lowest M bits of new N-bit digital output signal, directly taking N-th to (M+1)-th bits of previous N-bit digital output signal as N-th to (M+1)-th bits of new N-bit digital output signal, and repeating steps 3) and 4) until the analog input signal is fully sampled and converted. Required cycles can be reduced resulting in higher conversion rate and lower power consumption.

Successive approximation register analog-to-digital converter and conversion method therefor

A dummy pattern filling method, including: Step I, determining the rule of filling dummy patterns, in accordance with required DR values and isolation rules of patterns; Step II, finding out blank Fields within said layout that need to be filled with dummy patterns; Step III, by following said rule of filling dummy patterns, filling dummy patterns within blank Fields on layouts. Implementing a Smart Dummy Pattern Filling, which enables the Data Ratio (DR) of dummy patterns to come infinitely close the required DR value after completing the filling of dummy patterns.

Dummy pattern filling method

A flash memory unit, a memory array and operation methods thereof are provided. The flash memory unit includes a semiconductor substrate, a first and a second bit line structures, a word line structure, a first and a second float gates, and a first and a second control gates. The semiconductor substrate has doping wells formed therein, constituting a source and a drain. The first and second bit line structures are respectively connected with the source and the drain. The word line structure is disposed between the first and second bit line structures. The first float gate is disposed between the first bit line structure and the word line, and the second float gate is disposed between the second bit line structure and the word line. The first control gate is disposed on the first float gate, and the second control gate is disposed on the second float gate.

Flash memory unit and memory array, and programming, erasing and reading method thereof

A memory includes an array of memory cells including a plurality of memory cells with a common source, wherein each of the plurality of memory cells with a common source includes two sub-memory cells, each of the sub-memory cells corresponds to a bit line, and the respective bits are electrically independent. Each of the sub-memory cells in the memory according to the disclosure corresponds to a bit line, and the respective bit lines are electrically independent, thereby effectively avoiding interference to other memory cells which will not be programmed during a program operation.

Memory and method of operating the same

A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.

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Shanghai, China

Weiran Kong