Lsi Corporation

Lsi Logic Corporation

Weiqing Guo

Sandeep Bhutani

Payman Zarkesh-Ha

Ivan Pavisic

Qian Cui

Oian Cui

An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. the elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.

Moment computation algorithms in VLSI system

A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.

Probabilistic noise analysis

An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. The elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.

Reducing a parasitic graph in moment computation algorithms in VLSI systems

A system for estimating stage delay in an integrated circuit design includes steps of receiving as input an integrated circuit design including a single stage having at least two inputs, an output, and an interconnect connected to the output; calculating a separate interconnect delay for the interconnect as a function of an input ramptime for each of the inputs; adding a gate delay of each of the inputs to the separate interconnect delay calculated as a function of the input ramptime to estimate a stage delay for each of the inputs; and generating as output the stage delay for each of the inputs.

System for avoiding false path pessimism in estimating net delay for an integrated circuit design

A method of computing output delay in a mathematical model of an integrated circuit by sorting cells of original design of an the integrated circuit in a topological order. The original output delays for the sorted cells in the original design are computed in the topological order, to produce original output ramp times. The original output ramp times are propagated and original output delays are computed, and the original output ramp time and original output load for each cell is stored. The cells of the original design are modified to produce a modified design. For each modified cell in the topological order, a new output delay and a new output ramp time are computed and compared to the original output ramp time on the modified cell. When the new output ramp time substantially equals the original output ramp time for a modified cell, the calculations of the modified output ramp time for cells that are further down in the topological order are stopped. Otherwise the calculations of the modified output ramp time for cells that are further down in the topological order are continued until a cell is reached where the new output ramp time substantially equals the original output ramp time.

Delay computation speed up and incrementality

Method for reducing a parasitic graph in moment computation in VLSI systems

A method includes steps of: (a) receiving as input a waveform of a transient signal as a function of time for an aggressor net; (b) finding a peak value of the waveform and a corresponding peak time of the waveform propagated from the aggressor net to a victim net; (c) defining a selected time interval within the waveform at the victim net that includes the peak value and excludes features of the waveform not associated with the peak value wherein the selected time interval begins at a first time and ends at a second time; (d) calculating a weighted value of a function of the waveform at the first time and the second time; (e) calculating a local average value of the waveform as a function of the peak value and the weighted value; and (f) generating as output the local average value of the waveform.

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Fremont, CA, United States of America

Weiqing Guo