Intel Corporation

Weiqiang Ma

Ned M Smith

Francesc Guim Bernat

Kshitij Arun Doshi

Rita H Wouhaybi

Srikathyayani Srikanteswara

Timothy Verrall

Stephen T Palermo

Marcos Emanuel Carranza

Yi Zhang

Neelam Chandwani

Thijs Metsch

Cesar Martinez-Spessot

Nitin N Garegrat

Naveen Lakkakula

Atul Kwatra

Zdenek A Brun

David A Smiley

Justin B Diether

Various approaches for the packet processing, and the use of templates for generating modification commands for packet processing, are discussed herein. In an example, operations performed by network packet processing circuitry include: obtaining a stream of packets; obtaining a packet modification template that provides at least one command to insert content within the packets and change the packets according to an output format of a network protocol; receiving parameters to modify the packet modification template; and applying the packet modification template to modify the packets. In further examples, application of the packet modification template is performed using multiple processing components arranged in parallel groups of serial pipelines, each of the serial pipelines applying a portion of the packet modification template within at least a first stage and a second stage in each of the serial pipelines.

Network processor with command-template packet modification engine

A processing engine implementing job arbitration with ordering status is disclosed. A method of the disclosure includes receiving, by a job assigner communicably coupled to a plurality of processors, availability status from a plurality of job rings, availability status from the plurality of processors, and job entry completion status from an order manager, identifying, based on the received job entry completion status, a set of job rings from the plurality of job rings that do not exceed threshold conditions maintained by the job assigner, selecting, from the identified set of job rings, a job ring from which to pull a job entry for assignment, wherein the selecting is based on the received availability status of the plurality of job rings, and selecting, based on the received availability status of the plurality of processors, a processor to receive the assignment of the job entry for processing.

Processing engine implementing job arbitration with ordering status

Data represented by a received point which is not within a boundary of a signal constellation having a set of points is obtained by comparing the received point to less than all of the points on a boundary of the signal constellation. In an embodiment, the received point is compared to no more than two points on the boundary which have been predetermined to be the closest to the received point.

Signal constellation slicer

A system and method for limiting the processing load on a digital processor in a block processing modem that is receiving data that was generated from the digital to analog clock of the remote transmit modem having a frequency that may be different than the frequency of the analog to digital clock in the local receiving modem. The receiving modem includes a digital processor having a desired processing capacity reserved for block processing of L samples of data per block period, an analog to digital converter for converting the received data into samples, an interpolator and a buffer memory. The analog to digital converter outputs L-A samples per block and passes them to the interpolator, where A.gtoreq.1. The interpolator processes L-B samples per block and passes them on to the buffer, where B.gtoreq.0. The buffer passes L samples per block to the modem processor. If L samples are not available, the processor skips a cycle. The invention also contemplates a modem transmitter that includes a buffer that receives L samples per block from the digital processor and supplies a block of size L-A samples to a digital to analog converter. The buffer accumulates A samples on each block transfer and when there are L-A samples in the buffer, a block of L-A samples is passed without receiving any additional samples from the digital processor.

System and method for reducing the peak load on the processor of a block

A system and method for limiting the processing load on a digital processor in a block processing modem that is receiving data that was generated remotely using a clock having a frequency that may be different than the frequency of the clock in the receiving modem. The receiving modem includes a digital processor having a desired processing capacity reserved for block processing of L samples of data per block period, an analog to digital converter for the received data into samples, an interpolator and a buffer memory. The analog to digital converter outputs L-A samples per block and passes them to the interpolator, where A.gtoreq.1. The interpolator processes L-B samples per block and passes them on to the buffer, where B.gtoreq.0. The buffer passes L samples per block to the modem processor. If L samples are not available, the processor skips a cycle. The inventor also contemplates a modem transmitter that includes a buffer that receives L samples per block from the digital processor and supplies a block of size L-A samples to a digital analog converter. The buffer accumulates A samples on each block transfer and when there are L-A samples in the buffer, a block of L-A samples is passed without receiving any additional samples from the digital processor.

Growing community of inventors

Tempe, AZ, United States of America

Weiqiang Ma