Altera Corporation

Xilinx, Inc.

Weiqi Ding

Sergey Yuryevich Shumarayev

Wilson Wong

Tim Tri Hoang

Mingde Pan

Peng T Li

Thungoc M Tran

Wei Li

Yanjing Ke

Allen K Chan

Masashi Shimanouchi

Ali Atesoglu

Warren Nordyke

Mengchi Liu

Richard G Cliff

Yan Chong

Tien Duc Pham

Bonnie I Wang

Jon M Long

Shuxian Chen

Albert Ratnakumar

Kumara Tharmalingam

Jie Shen

Shou-Po Shih

Sriram Narayan

Sangeeta Raman

Donald W Alderrou

Mike Peng Li

Joel Martinez

Richard Hernandez

Sharat Babu Ippili

Juei-Chu Tu

Qi Xiang

David Wolk Mendel

Jeffrey T Watt

Gregg William Baeckler

Kyung Suk Oh

Amitava Majumdar

Simardeep Maangat

Ning Xue

Mei Luo

Michael Menghui Zheng

Pradeep Nagarajan

Jeffrey Xiaoqi Tung

Sean Shau-Tu Lu

Peng Li

Yujeong Shim

Xiong Liu

Toan Thanh Nguyen

Xudong Shi

Binh Ton

Daniel Tun Lai Chow

Gopi Krishnamurthy

Rambabu Nerukonda

Sunitha Chandra

Haidang Lin

James Kimble Lin

Siriram Narayan

Lewelyn Mark D'Souza

Mengchi Lui

Bhuvanachandran K Nair

A transceiver circuit is disclosed, the transceiver circuit including a first register circuit, configured to receive serial stimulus data and to generate multi-bit parallel stimulus data, a serializer circuit configured to receive the multi-bit parallel stimulus data and to generate serialized data based on the multi-bit parallel stimulus data, where the serializer circuit includes a serializer data storage device, and where the serializer data storage device lacks circuit structures for scanability, a deserializer circuit configured to receive serial receiver data corresponding with the serialized data and to generate multi-bit parallel response data based on the serial receiver data, where the deserializer circuit includes a deserializer data storage device, and where the deserializer data storage device lacks circuit structures for scanability, and a second register circuit, configured to receive the multi-bit parallel response data and to generate serial response data.

Transceiver loopback testing

Systems and methods are provided to improve flexibility of optical signal transmission between integrated circuit devices, and more specifically data utilization circuits. More specifically, the integrated circuit devices may include a data utilization circuit communicatively coupled to a field programmable optical array (FPOA). In some embodiments, the FPOA may convert an electrical signal received from the data utilization to an optical signal, route the optical signal to an optical channel, and multiplex the optical signal with other optical signals routed to the optical channel. Additionally or alternatively, the FPOA may de-multiplex a multiplexed optical signal based on wavelength, route an optical signal included in the multiplexed optical signal to an electrical channel, convert the optical signal into an electrical signal, and output the electrical signal to the data utilization circuit via an electrical channel. In some embodiments, the FPOA may improve flexibility by performing such functions without reconfiguring the data utilization circuit.

Integrated circuit device with field programmable optical array

A clocking arrangement for transceivers in an integrated circuit device includes a plurality of fractionally adjustable phase-locked loops. Each respective one of the fractionally adjustable phase-locked loops generates a respective transmit frequency for a respective one of the transceivers. There is a respective clock-data recovery module in a receive portion of each respective one of the transceivers, and each respective clock-data recovery module includes a respective fractionally adjustable frequency-lock loop. There is a reference clock input providing a reference clock for a plurality of the fractionally adjustable phase-locked loops and the fractionally adjustable frequency-lock loops. The reference clock input can be a sole reference clock input providing a reference clock for all of the adjustable phase-locked frequency-lock loops. Alternatively, the reference clock input can include a plurality of separate reference clock inputs, each providing a separate reference clock to a predetermined subset of the adjustable phase-locked or frequency-lock loops.

Reference clock architecture for integrated circuit device

Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

High-speed serial data signal receiver circuitry

One embodiment relates to a method of automated adaptation of a transmitter equalizer. A multi-dimensional search space of tap settings for the transmitter equalizer is divided into multiple single-dimensional search spaces, each single-dimensional search space being associated with a single tap of the transmitter equalizer. The multiple single-dimensional search spaces are searched in series, and a tap for a single-dimensional search space is set before searching a next single-dimensional search space. Another embodiment relates to a transceiver with adaptation circuitry configured to implement the above-described method. Other embodiments, aspects, and features are also disclosed.

Methods and apparatus for automated adaptation of transmitter equalizer tap settings

Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g.,parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Another embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit including a first strip of PLL circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. Other embodiments and features are also disclosed.

Phase-locked loop architecture and clock distribution system

An integrated circuit package includes an interposer with an embedded clock network formed by multiple clock trees. A die with first and second clock circuits is disposed over the interposer. At least one of the first and second clock trees is a resonant clock tree and both the first and second clock circuits may provide clock signals at different frequencies. The first clock circuit may provide clock signals at one frequency to a clock tree in the embedded clock network while the second clock circuit may provide clock signals at another frequency to another clock tree in the embedded clock tree network.

Interposer with embedded clock network circuitry

One embodiment relates to a receiver circuit for a data link. The receiver circuit includes at least a first signal path, a second signal path, and a path selector circuit. The first signal path includes first equalization circuitry, and the second signal path includes second equalization circuitry. The path selector circuit is configured to select one signal path of the first and second signal paths. Other embodiments and features are also disclosed.

Flexible receiver architecture

An analog test network includes a conductor. The conductor is coupled to provide a first analog signal from a circuit under test to an analog-to-digital converter circuit. The analog-to-digital converter circuit is operable to generate a first digital signal based on the first analog signal. A control circuit is operable to generate a second digital signal based on the first digital signal. A digital-to-analog converter circuit is operable to generate a second analog signal based on the second digital signal. The conductor is coupled to provide the second analog signal from the digital-to-analog converter circuit to the circuit under test.

Analog signal test circuits and methods

Integrated circuits may include memory interface circuitry operable to communicate with system memory. The memory interface circuitry may receive data (DQ) and data strobe (DQS) signals from system memory during read operations. The memory interface circuitry may include startup calibration circuitry and runtime calibration circuitry. The startup calibration circuitry may be used upon device startup to perform a one-time data de-skew and DQ/DQS centering. The runtime calibration circuitry may include at least two data sampling circuits, a first of which is used in active mode to latch incoming data and a second of which is used in redundant mode to obtain data eye boundary information on a continuous basis. The received DQS signal may be adjusted based on the obtained eye boundary information so that DQS properly positioned within the data eye periodically or on an as-needed basis.

Methods and apparatus for performing runtime data eye monitoring and continuous data strobe calibration

One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Each PMA module includes multiple CDR circuits, receives multiple serial data signals, and outputs data from those signals in parallel form. The programmable clock network allows the reference clock signals to be selectively shared by the PMA modules and the multiple-purpose PLLs. Another embodiment relates to a method of providing clock signals for multiple purposes in an integrated circuit. Clock signals are generated by a plurality of multiple-purpose PLLs and are selectively distributed to PMA modules arranged at a side of the integrated circuit and to logic circuitry arranged in a core section of the integrated circuit. The clock signals are used by circuitry in the PMA modules for supporting a plurality of data communications channels. Other embodiments and features are also disclosed.

Growing community of inventors

Fremont, CA, United States of America

Weiqi Ding