Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

Weining Li

Jia Zhen Zheng

Pradeep Yelehanka

Elgin Kiok Quek

Tommy Lai

Tze Ho Simon Chan

Yung-Tao Lin

Yung Tao Lin

Tin Tin Wee

Juan Boon Tan

Wanbing Yi

Hai Cong

Kin Wai Tang

Chin Chuan Neo

Ramachandramurthy Pradeep Yelehanka

Mau Lam Lai

Lin Yung Tao

Tommy Mau Lam Lai

A semiconductor device and method for forming a semiconductor device are presented. The method includes providing a patterned reticle having a pattern perimeter defined by active and dummy patterns. The dummy patterns include dummy structures modified according to a density equation. The patterned reticle is used to pattern a resist layer on a substrate with a device layer. An etch is performed to pattern the device layer using the patterned resist layer. Additional processing is performed to complete formation of the device.

Etch bias control

A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.

Non-volatile memory manufacturing method using STI trench implantation

An integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.

Integrated circuit with protected implantation profiles and method for the formation thereof

An integrated circuit structure includes a semiconductor substrate and a horizontal semiconductor fin on top of the semiconductor substrate. An access transistor gate and a thyristor gate are on top of the semiconductor substrate and in contact with the horizontal semiconductor fin. An access transistor is at least a portion of the horizontal semiconductor fin and the access transistor gate. A thyristor is at least a portion of the horizontal semiconductor fin and the thyristor gate, the access transistor is in contact with the thyristor.

Thyristor-based SRAM

An integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

Horizontal tram

An integrated circuit structure includes a semiconductor substrate and a thyristor formed thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

Horizontal TRAM and method for the fabrication thereof

A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.

A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a gate dielectric layer over the semiconductor substrate. The gate dielectric layer is formed in a plurality of thicknesses in a plurality of devices regions over the semiconductor substrate. A second dielectric layer is formed over at least one of the devices regions. A third dielectric layer is formed over at least a portion of the second dielectric layer. Ion traps are then selectively implanted in portions of the second dielectric layer.

Multi-level gate SONOS flash memory device with high voltage oxide and method for the fabrication thereof

A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a horizontal semiconductor fin on top of the semiconductor substrate. An access transistor gate and a thyristor gate are then formed on top of the semiconductor substrate and in contact with the horizontal semiconductor fin. An access transistor is formed from at least a portion of the horizontal semiconductor fin and the access transistor gate. A thyristor is formed from at least a portion of the horizontal semiconductor fin and the thyristor gate, the access transistor being in contact with the thyristor.

Method using quasi-planar double gated fin field effect transistor process for the fabrication of a thyristor-based static read/write random-access memory

A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a thyristor thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

Thyristor-based SRAM and method for the fabrication thereof

A new angle implant is provided that reduces or eliminates the effects of narrow channel impurity diffusion to surrounding regions of insulation. The invention provides for angle implantation of p-type impurities into corners of STI regions that are adjacent to NMOS devices and angle implantation of n-type impurities into corners of STI regions that are adjacent to PMOS devices.

Method of angle implant to improve transistor reverse narrow width effect

An improved and new process for fabricating self-aligned contacts (SAC) to source/drain areas of complimentary (CMOS) FET's has been developed using a non-conformal layer of silicon nitride, eliminating the need for a hard mask. This process allows for &ldquo;zero&rdquo; spacing from contact structure to polysilicon gate structure, for closely spaced design rule gates. Some key process features of this invention are as follows: no hard mask is needed and the gate process is exactly the same as &ldquo;standard&rdquo; logic process. The process differences are that between the S/D implant, salicidation and the normal contact process, there is inserted a non-conformal CVD silicon nitride deposition with a SAC pattern and etch process. The process is fully compatible with both state of-the-art salicide and polycide processes. The self-aligned contact process simplifies processing, while yielding improvements in electrical device performance and reliability. The process is very useful for the &ldquo;standard&rdquo; logic device salicided processes.

Method for making self-aligned contacts to source/drain without a hard mask layer

A new method of forming MOS transistors with self-aligned silicide has been achieved. A gate oxide layer is formed overlying a semiconductor substrate. A polysilicon layer is deposited. The polysilicon layer and the gate oxide layer are patterned to form gates. Ions are implanted to form lightly doped drain regions. A dielectric layer is deposited. The dielectric layer is polished down to expose the top surface of the gates. The dielectric layer is then anisotropically etched down to form dielectric sidewall spacers. The dielectric sidewall spacers cover a portion of the vertical sidewalls of the gates while exposing a portion of the vertical sidewalls of the gates. Ions are implanted to form source and drain regions. A metal layer is deposited. Contact surfaces are formed between the metal layer with: the exposed top surfaces of the gates, the exposed portions of the vertical sidewalls of the gates, and the exposed source and drain regions. The integrated circuit device is annealed to react the metal layer and the polysilicon layer and silicon to selectively form a silicide layer in the surface of the polysilicon layer and in the surface of the semiconductor substrate at the contact surfaces. The remaining metal layer is removed to complete the device.

Method to form self-aligned silicide with reduced sheet resistance

A method for integrating salicide and self-aligned contact processes in the fabrication of integrated circuits by using a poly cap mask and a special layout technique is described. A pair of gate electrodes and associated source and drain regions are formed overlying a semiconductor substrate wherein nitride spacers are formed on sidewalls of the gate electrodes. A poly-cap layer is deposited overlying the gate electrodes and source and drain regions. The poly-cap layer is selectively removed overlying one of the source and drain regions between the gate electrode pair where a self-aligned contact is to be formed and removed over one of the gate electrode pair. An insulating layer is deposited over the surface of the semiconductor substrate. The planned self-aligned contact opening is made through the insulating layer to the source/drain region to be contacted wherein the contact opening partially overlies the poly-cap layer over the adjacent gate electrode of the pair. The self-aligned contact opening is filled with a conducting layer to complete fabrication of the integrated circuit device.

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Shanghai, China

Weining Li