Huawei Technologies Co., Limited

Intel Corporation

Weinan Li

Wei Zhang

Tao Liu

Jian Liang

Yan Zhao

Zhi Wang

Yongchang Yu

Xiaoran Li

Min Yi

This application provides an operational amplifier and a start-up circuit of the operational amplifier. The start-up circuit has the advantages of having a simple structure and consuming less. The operational amplifier includes a multi-stage amplifier and a start-up circuit, where the start-up circuit includes a first start-up transistor and a second start-up transistor. A source of the first start-up transistor and a source of the second start-up transistor are connected to a tail bias node of a first-stage amplifier in the multi-stage amplifier, a gate of the first start-up transistor and a gate of the second start-up transistor are configured to connect to a first bias voltage V, and a drain of the first start-up transistor and a drain of the second start-up transistor are connected to input terminals of a second-stage or higher-stage amplifier.

Operational amplifier and start-up circuit of operational amplifier

An apparatus and method for scheduling workloads across virtualized graphics processors. For example, one embodiment of a graphics processing apparatus comprises first graphics processing resources to process graphics commands and execute graphics data; workload scheduling circuitry to schedule workloads for execution on the first graphics processing resources; and workload queuing circuitry to implement a local queue to store local workload entries, each local workload entry associated with a locally-submitted workload and an external workload queue to store external workload entries, each external workload entry associated with an externally-submitted workload submitted for execution by an external graphics processing apparatus, in one embodiment, the workload scheduling circuitry schedules the locally-submitted workloads identified in the local queue and externally-submitted workloads identified in the external workload queue for processing by specified portions of the first graphics processing resources.

Apparatus and method for scheduling graphics processing resources

Systems, apparatuses and methods may provide for technology that sets a write protection flag in a guest command buffer associated with a virtual machine and injects a semaphore command into a shadow command buffer in response to a fault. The fault is to correspond to a write of a graphics command to the guest command buffer by code executing in graphics hardware. In one example, the technology also conducts a security scan of the graphics command in response to a context switch in the graphics hardware, wherein the context switch is to be associated with the semaphore command.

Supporting self-modifying graphics workloads in fully virtualized graphics architectures

An embodiment of a semiconductor package apparatus may include technology to manage one or more virtual graphic processor units, and co-schedule the one or more virtual graphic processor units based on both general processor instructions and graphics processor instructions. Other embodiments are disclosed and claimed.

Hybrid virtual GPU co-scheduling

A diversity receiver and a terminal are provided. The diversity receiver includes a first main channel and a first diversity channel, the first main channel includes an antenna diplexer and a first main transmission channel, and the first diversity channel includes a tunable bandpass filter and a first diversity receiving channel. The first diversity receiving channel is coupled to a diversity antenna by using the tunable bandpass filter, and the tunable bandpass filter is configured to: adjust a passband bandwidth of the tunable bandpass filter according to a band bandwidth of a first transmit signal generated by the first main transmission channel and a band bandwidth of a first receive signal received from the diversity antenna, and perform bandpass filtering based on the passband bandwidth on the first receive signal.

Diversity receiver and terminal

The present application discloses a diversity receiver and a terminal. The diversity receiver includes a first main channel and a first diversity channel, the first main channel includes an antenna diplexer and a first main transmission channel, and the first diversity channel includes a tunable bandpass filter and a first diversity receiving channel. The first diversity receiving channel is coupled to a diversity antenna by using the tunable bandpass filter, and the tunable bandpass filter is configured to: adjust a passband bandwidth of the tunable bandpass filter according to a band bandwidth of a first transmit signal generated by the first main transmission channel and a band bandwidth of a first receive signal received from the diversity antenna, and perform bandpass filtering based on the passband bandwidth on the first receive signal.

A switch, an antenna tuner, and a radio frequency apparatus are provided. The switch includes: 2N successively serially connected transistors. In the 2N successively serially connected transistors, control ends of any two transistors with closest odd sequence numbers are coupled to each other through a first resistor, and control ends of any two transistors with closest even sequence numbers are coupled to each other through a second resistor; a control end of an n-th transistor is coupled to a first control signal in a switch control signal, and a control end of an (n+1)-th transistor is coupled to the first control signal, where n is an integer that is greater than or equal to 1 and is less than or equal to 2N&#x2212;1, N is an integer greater than or equal to 2, and the first control signal is used to control turn-on or turn-off of the switch.

Switch, antenna tuner, and radio frequency apparatus

A radio frequency circuit. In the circuit, a first directional coupler receives a second transmit signal, uses a part of the second transmit signal as a third transmit signal, directly sends the third transmit signal to a first port of a circulator, and obtains a first coupling signal from the second transmit signal; the circulator outputs the third transmit signal through a second port; an impedance tuner transmits the third transmit signal to an antenna port and transmits, to the second port of the circulator, a first input signal from the antenna port; the circulator inputs the first input signal to a second directional coupler through a third port; the second directional coupler obtains a second coupling signal from the first input signal; and a controller adjusts impedance of the impedance tuner according to the first coupling signal and the second coupling signal.

Radio frequency circuit and mobile terminal

The present invention provides an antenna impedance matching apparatus, semiconductor chip, and method. The apparatus includes: a semiconductor chip, including multiple adjustable capacitors and multiple switches; and at least one impedance component, located outside the semiconductor chip, where the semiconductor chip is coupled to the at least one impedance component through multiple terminals and coupled to an input terminal and an output terminal of the antenna impedance matching apparatus, the input terminal and the output terminal of the antenna impedance matching apparatus are respectively coupled to a radio frequency circuit and an antenna, the multiple switches are configured to, under control of a control signal, switch a connection between the multiple adjustable capacitors and the at least one impedance component, and values of the multiple adjustable capacitors are adjusted by an adjustment signal, so as to tune impedance matching of the antenna.

Growing community of inventors

Shanghai, China

Weinan Li