Conexant Systems, Inc.

Nxp B.v.

International Business Machines Corporation

Weinan Gao

Ray Rosik

Mark Santini

Mats Lindstrom

Jianhua Lu

Damian Costa

Ramkishore Ganti

Aria Eshraghi

A wideband RF tracking filter having a set of parallel tuned resonator amplifier stages with a de-Q resistor for each subband is disclosed. The resonant amplifier contains programmable tuned LC tank impedance and an array of parallel voltage to current converters (V2I) for each subband. The de-Q resistor together with the array of V2I converters provides a flat gain over each subband and each of the other subbands covering different frequencies.

Integrated wideband RF tracking filter for RF front end with parallel band switched tuned amplifiers

Systems and methods are provided. In this regard, a representative system incorporates a crystal oscillator circuit and a digital automatic level control circuit. The digital automatic level control circuit is operative to: convert an oscillation amplitude of the crystal oscillator circuit to a proportional DC voltage; convert the DC voltage to a corresponding digital code representation; and adjust bias current and oscillator loop gain such that a desired oscillation amplitude is set.

Systems and methods with reduced reference spurs using a crystal oscillator for broadband communications

Systems and methods for providing bias currents to multiple analog circuits are disclosed. An integrated circuit comprises a calibration circuit which compares a high tolerance external component to a plurality of internal components manufactured to span the variability of the process, voltage and temperature. The best fitting internal component is communicated to bias circuits which can select an internal component from a local plurality of internal components with matching desired characteristics. In this manner, analog circuits can be locally biased with the tolerance usually associated with a high tolerance external reference component, without the necessity for a local external reference component.

Method and algorithm of high precision on-chip global biasing using integrated resistor calibration circuits

Systems for suppressing image noise are provided. In this regard, one embodiment includes a system for suppressing image noise comprising a low noise amplifier (LNA) configured to amplify a received RF signal, an RF variable gain attenuator with an image rejection filter with programmable bandwidth configured to suppress image noise and image interference, and an RF mixer configured to perform frequency translation.

Systems and methods for reducing broadband image noise through a programmable bandwidth RF variable gain attenuator

A mixer for use in a transceiver comprises an LO switching pair and a folded transconductor. The mixer can be used as an upconversion or down conversion mixer and provides increased headroom and linearity, while still reducing current consumption. The mixer can be configured for differential inputs and outputs and the folded transconductor can comprises a MOSFET differential pair.

Systems and method for a highly linear, low power mixer

A DC offset correction system for a direct-conversion receiver is disclosed that may include a DC feedback correction servo-loop in signal communication with a baseband section, where the DC feedback correction servo-loop is coupled to both the input and output of the baseband section and an attenuator within the DC feedback correction servo-loop.

DC offset correction for direct-conversion receiver

An automatic quadrature phase compensation system comprises an on-chip analog phase sense circuit capable of detecting small differences in quadrature phase error and providing a corresponding DC voltage, a voltage-controlled or programmable phase delay circuit to implement quadrature phase error correction, and a feedback system or compensation engine used to process the sensed error voltage and apply a corresponding correction signal to the adjustable phase delay.

Systems and method for automatic quadrature phase imbalance compensation using a delay locked loop

A continuous time delta-sigma analog to digital converter is disclosed. A summing junction receives an input analog signal to be digitized and a feedback signal. A loop filter receives the combined signals from the summing junction, and a course analog to digital converter converts the combined signal to a multi-bit digital number. A sin DAC provides a feedback signal to the summing junction, by reconverting the multi-bit digital signal to an analog signal. The sin DAC produces a linear output signal having a reduced phase jitter, resulting in a lower noise floor for the multi-digital signal. The sin DAC may be an NRZ sin DAC which avoids stringent linearity requirements on the summing junction.

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San Diego, CA, United States of America

Weinan Gao