Semiconductor Components Industries, LLC

Fairchild Semiconductor Corporation

WeiMing Sun

Lei Huang

Peng Zhu

Jianli Chen

Emma Wang

Eric Wu

Ming Chuen Alvan Lam

Zhaohong Li

Hong Bing Wu

Leon Li

Young Liang Li

In a general aspect, a discharge circuit for discharging a voltage from a USB connector pin can include a discharge load configured to discharge the voltage from the pin. The discharge circuit can also include a first control circuit configured to adjust a magnitude of the discharge load during discharging, such that power consumption is less than or equal to a discharge power limit, and a discharge time is less than or equal to a discharge time limit. The discharge circuit can further include a second control circuit configured to detect whether the voltage of the pin is changed based on a first reference voltage during discharging and adjust the magnitude of the discharge load in response to the change in the voltage of the pin, such that a slew rate of the voltage is less than or equal to a slew rate limit.

Discharge method and circuit for USB connector

This document discusses, among other things, a signal receiving circuit, configured to receive an input voltage signal. The signal receiving circuit can comprise an input voltage regulating circuit and a comparing circuit. The input voltage regulating circuit can carry out a waveform pre-regulation for the input voltage signal to obtain a first voltage signal, and the comparing circuit can compare the first voltage signal with a second voltage signal, and output a comparison voltage signal having a pulse width that satisfies a first predetermined condition indicative that the input voltage signal is correctly identifiable. The present document further discusses a signal detecting circuit and a signal receiving method.

Signal receiving circuit and method, and signal detecting circuit

According to an aspect, a switch circuit for a Universal Serial Bus (USB) connector device includes a main transistor configured to be activated during a normal operation of the switch circuit, a first voltage generator circuit configured to generate a voltage on a high local rail during an overvoltage event, a second voltage generator circuit configured to generate a voltage on a low local rail during the overvoltage event, where the low local rail is connected to a bulk of the main transistor, and a clamp circuit connected to the high local rail between the first voltage generator circuit and a gate of the main transistor, where the clamp circuit is configured to clamp the voltage between the high local rail and the gate of the main transistor during the overvoltage event.

Switch circuit with high voltage protection that reduces leakage currents

According to an aspect, an overvoltage protection circuit includes a bias current generator configured to generate a bias current, and a current comparator configured to receive the bias current and a voltage associated with a data terminal of a connector. The current comparator includes a transistor. The transistor is configured to activate based on a level of the voltage associated with the data terminal. The current comparator is configured to compare a current of the transistor with the bias current. The overvoltage protection circuit includes an output circuit configured to generate an overvoltage protection signal in response to the current of the transistor being greater than the bias current.

Overvoltage protection circuit for USB connector

In a general aspect, a circuit can include a reference current generator configured to generate a first current signal representative of a threshold voltage. The circuit can also include a current comparator configured to mirror the first current signal, generate a second current signal representative of a received voltage and compare the second current signal to the first current signal. The current comparator can also be configured to provide a detection signal at a first logic value to indicate that the received voltage is below the threshold voltage when the comparison of the second current signal with the first current signal indicates that the received voltage is less than the threshold voltage.

Negative voltage detection and voltage surge protection

A circuit for power supply protection comprising a first n-channel Metal Oxide Semiconductor Field Effect Transistor (nMOSFET) and a first p-channel Metal Oxide Semiconductor Field Effect Transistor (pMOSFET) each having a drain terminal coupled to an input voltage, a second nMOSFET and a second pMOSFET having drain terminals coupled to an output voltage and sources coupled to a sources of the first and second nMOSFET, respectively, and a control circuit. The control circuit turns the nMOSFETs off and the pMOSFETs on when the input voltage has a voltage value greater than zero and less than a predetermined positive limit, operates the nMOSFETs in a saturation mode and turns the pMOSFETs off when the input voltage has a voltage value greater than the predetermined positive limit, and turn the nMOSFETs and pMOSFETs off when the input voltage has a voltage value less than zero.

High voltage clamp with positive and negative protection

This document discusses, among other things, a discharge circuit for a USB connector configured to discharge a voltage of a pin (e.g., a VBUS pin) of the USB connector. The discharge circuit can include a discharge load to discharge the voltage of the pin; a first control circuit to adjust the magnitude of the discharge load during discharging, such that power consumption generated by the discharge load meets a first preset condition and a discharge time is within a first preset range, the first preset condition indicating that the generated power consumption does not trigger Over Temperature Protection (OTP); and a second control circuit to detect whether the voltage of the pin is changed based on a reference voltage during discharging and adjust the magnitude of the discharge load in response to the change, such that a slew rate of the voltage of the first pin is within a second preset range.

Systems and methods are disclosed, including a USB interface detector, a detection method, a USB connector, and an electronic device. The detection method may be applicable to the USB connector mounted in the electronic device. According to an operation mode of the electronic device, a first pin and a second pin in the USB interface can be pulled up or pulled down. After the pull up or the pull down, a voltage change at the first and second pins are detected. If the voltage changes cross a reference voltage, an instruction related to attachment or detachment with a second device can be provided.

USB interface detector

A delay time adjusting circuit is described, in which a reference signal circuit generates at least one reference signal to an A/D conversion circuit, an input signal circuit generates an input signal to the A/D conversion circuit, the A/D conversion circuit compares the input signal with the at least one reference signal to output a digital signal to a digital logic chip, and the digital logic chip determines a delay time based on the digital signal. In this way, the delay time can be determined digitally, and an adjusting accuracy of the delay time can be increased; and also, the delay time can be adjusted through changing the level of the input signal, thus reducing circuit losses and costs.

Delay time adjusting circuit, method, and integrated circuit

This document discusses, among other things, a delay circuit, in which a first register is written with a delay reference code, a second register is written with a delay factor, a control unit determines a corresponding delay ratio in a storage unit based on the delay factor in the second register, and sends the determined delay ratio to a first digital timing unit, the first digital timing unit determines a delay reference time based on the delay reference code in the first register, multiplies the delay reference time by the delay ratio to result in a desired delay time, and generates a delay.

Delay method, circuit and integrated circuit

An embodiment of an input-buffer circuit may include an input stage with an inverter having an input operable to receive a signal to be translated. The input stage may include a limiting circuit coupled to the input stage for arresting quiescent current. Additional embodiments of an input-buffer circuit formed according to the subject matter disclosed herein may include feedback transistors suited to provide additional current to the input stage and a hysteresis circuit suited to provide hysteresis current to the input stage when an input signal has a high-frequency change rate.

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Beijing, China

WeiMing Sun