Broadlogic Network Technologies Inc.

Mie Fujitsu Semiconductor Limited

Broadcom Corporation

Altera Corporation

Intel Corporation

Avago Technologies International Sales Pte. Limited

Suvolta, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Weimin Zhang

Lucian Shifren

Scott E Thompson

Pushkar Ranade

Binfan Liu

Sachin R Sonkusale

Yanzhong Xu

Paul E Gregory

Bin-Fan Liu

Roger Stenerson

Junyi Xu

Jeremy Woodburn

Xuemin Chen

Yong Li

Vladimir Radionov

Thomas Ayers

Tim Misko

Yu Kou

Lance A Scudder

Thomas Hoffmann

Sameer S Pradhan

Teymur Bakhishev

Dalong Zhao

Sung Hwan Kim

Jing Wang

Michael Duane

Lingquan Wang

Victor Liang

Nelson Joseph Gaspard

Yujie Liu

Anthony Francesca

Zhongqiang Wang

Zhongqian Wang

Sricharan Kasetti

John S Chiu

Charlie Lei Lou

Sachrin R Sonkusale

Tony Francesca

A system for integrating video content and data provision includes an upstream signal path to process upstream data traffic received from a first transmission network for transmission to a second transmission network, and a downstream signal path to process downstream data traffic and downstream video traffic for transmission from the second transmission network to the first transmission network. The upstream signal path includes an analog-to-digital converter (ADC) and an upstream demodulator, and the downstream signal path includes an Ethernet processor, a digital-signal-processor (DSP) and a digital-to-analog converter (DAC).

Integrated video and data system

In some aspects, the disclosure is directed to methods and systems for providing coordinative security among network devices across multi-level networks. Shared cryptographic secrets among the network devices are used as the basis for mutual security authentication and peering among these devices. The cryptographic secrets can be embedded in the SoC devices for these devices or dynamically generated based on unique identification information and attributes of these SoC devices. The messages for authentication and peering can be communicated directly among the network devices or indirectly via a cloud security portal entity that acts as a messaging proxy. The mutual authentication and peering process can be carried out coordinately among the network devices and a cloud security portal in a one-to-one mesh relationship, or in a transitive layering relationship, where each network entity authenticates and peers with its direct subordinates in a multi-level network.

System for coordinative security across multi-level networks

An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5&#xd7;10dopant atoms per cm. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

Advanced transistors with punch through suppression

An integrated circuit is provided that includes memory elements that exhibit immunity to soft error upset (SEU) events when subjected to high-energy atomic particle strikes. Each memory element may include at least two inverting circuits coupled in a feedback loop. Transistors in the memory element may be grouped in one contiguous region or divided into multiple separate regions. The memory element may include a long gate conductor that extends outside the boundary of the one contiguous region or the multiple separated regions. The long gate conductor may serve to provide parasitic resistance in the feedback loop to help mitigate SEU disturbances.

Memory elements with soft-error-upset (SEU) immunity using parasitic components

An integrated circuit that includes an array of random-access memory cells is provided. Each memory cell may include inverting circuits formed from pull-up transistors and pull-down transistors and also access transistors coupled to the inverting circuits. The pull-up transistors may be formed in an n-well. The memory cells may also be coupled to single event latch-up (SEL) prevention circuitry. The SEL prevention circuitry may include a clamping circuit, a voltage sensing circuit, and a driver circuit. In response to a single event alpha particle strike at one of the memory cells, a temporary voltage rise may be presented at the clamping circuit. The voltage sensing circuit may detect the voltage rise and direct the driver circuit to bias the n-well into deep reverse bias region. Operated in this way, the SEL prevention circuitry can mitigate SEL while minimizing memory cell leakage.

Memory with single-event latchup prevention circuitry

A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced &#x3c3;Vcompared to conventional bulk CMOS and can allow the threshold voltage Vof FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.

Low power semiconductor transistor structure and method of fabrication thereof

The present disclosure is directed to a system and method for creating overlapping bonded groups of downstream channels that can provide increased channel capacity to improve packing densities, while at the same time limiting complexity and cost increases of new receivers and allowing the continued operation of legacy receivers.

Method and system for efficient digital video transmission using bonded groups of channels

A method and apparatus for reducing global interconnect delay on a field programmable gate array (FPGA) on an integrated circuit die comprising coding with a digital to analog coder on the integrated circuit die successive groups of n digital bits into an 2level voltage or current signal where n is an integer greater than or equal to 2; transmitting the voltage or current signal on a global interconnect on the integrated circuit die; receiving on the integrated circuit die the signal transmitted on the global interconnect; and decoding the received signal on the integrated circuit die to reconstitute the successive groups of digital bits.

CMOS global interconnect using multi-voltage(or current)-levels

An illustrative finFET comprises first, second, and third pluralities of fins having gate structures and source and drain regions formed on the fins so that first PMOS transistors are formed in first epitaxial regions on the first plurality of fins, NMOS transistors are formed in second epitaxial regions on the second plurality of fins and second PMOS transistors are formed in third epitaxial regions on the third plurality of fins. In three embodiments, the fins are formed in silicon; the first epitaxial region is silicon germanium; the second region is silicon; and the third region is 1) silicon, 2) silicon carbide, or 3) silicon or silicon carbide on a silicon carbide cladding. In another embodiment, the third epitaxial regions are wide band gap semiconductors formed on wide band gap semiconductor fins. In another embodiment, all the fins and epitaxial regions are wide band gap semiconductors.

Low leakage FinFET

A bipolar junction transistor (BJT) is formed in a thin (less than about 20 nanometers) segment of a semiconductive material such as silicon where a lower portion of the semiconductive material has doping of a first conductivity type and forms a collector and an upper portion of the semiconductive material has doping of a second conductivity type and forms a base. Either a metal or a polysilicon emitter is formed on the base. An illustrative method for forming the BJT comprises forming first and second layers of a semiconductive material having first and second conductivity types, respectively; forming a hard mask on an upper surface of the second layer; using the hard mask to etch first and second channels in the semiconductive material on first and second opposing sides of the hard mask; removing the hard mask; and forming an emitter on the upper surface of the second layer.

Bipolar junction transistor

A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.

Deeply depleted MOS transistors having a screening layer and methods thereof

Methods, apparatuses, and systems are presented for switching between channels of encoded media data involving receiving encoded media data including reference frames and dependent frames for a plurality of channels, wherein each dependent frame refers to at least one reference frame. Frames associated with a first channel from the plurality of channels are decoded to generate a decoded signal for the first channel. While decoding frames associated with the first channel, data corresponding to at least one reference frame associated with a second channel from the plurality of channels are stored. In response to a control signal for switching from the first to the second channel, at least one dependent frame associated with the second channel is decoded by utilizing the stored data corresponding to the at least one reference frame associated with the second channel, to generate a decoded signal for the second channel.

Method and system for providing faster channel switching in a digital broadcast system

Growing community of inventors

San Jose, CA, United States of America

Weimin Zhang