Globespan Virata Corporation

Globespan, Inc.

Conexant Systems, Inc.

Weimin Liu

Ehud Langberg

Lujing Cai

Xiao Liu

Wenye Yang

Daniel Amrany

William H Scholtz

Farooq Jabbar

Xueming Lin

A system and method for performing pilot tone based timing recovery in a communication system using the discrete multi-tone (DMT) modulation. In DMT modulation, interference is introduced to the phase of the pilot tone in the transmitter due to the cyclic prefix. Broadly, a receiver is configured to detect and apply a phase offset to the pilot tone in a phase locked-loop upon recognition of far-end signal segments during transceiver initialization. The output of the phase locked-loop is then used to control the timing of the analog-to-digital (A/D) and digital-to-analog (D/A) conversions. In alternative embodiments, the receiver is configured to detect and remove the cyclic prefix from the far-end signal either prior to, or after, time-domain equalization. In a similar manner, the resulting signal stream is applied to the input of the timing recovery phase locked-loop (PLL). The output of the PLL is used to control the timing of the A/D and D/A converters. In a further alternative embodiment, a phase error on the pilot tone is estimated in the frequency domain. The phase error is then applied to the input of a modified timing recovery PLL to reduce phase interference on the pilot tone.

System and method for timing recovery in a discrete multi-tone system

The present invention is directed to a system and method for reducing the need to perform signal clipping in a DMT transmitter. In accordance with one aspect of the invention, a method performs an inverse Fourier Transform on the input to produce a time-domain, digital value to be transmitted to a remote receiver. The method then evaluates the magnitude of the digital value to determine whether the magnitude exceeds a threshold value. Then, the method alters the input and re-performs an inverse Fourier Transform on the altered input, only if the step of evaluating the magnitude determines that the magnitude of the digital value exceeds the threshold value.

System and method for reducing the effects of clipping in a DMT transceiver

The present invention generally relates to echo cancellation over an asymmetric transmission and receiving spectra. An apparatus is provided having a transmit path and a receive path, with an adaptive echo canceler disposed therebetween, for communicating data within a first bandwidth and a second bandwidth respectively. A first decimator is disposed between the transmit path and the echo canceler circuit and filters an incoming signal having a first sampling rate and emits a signal output at a second, reduced sampling rate. A second decimator is disposed along said receive path and filters an incoming signal and emits a signal output at a reduced sampling rate. An adder is disposed to subtract the output of the adaptive echo canceler from output of the second decimator to generate a received signal that is substantially free of echo.

System and method for echo cancellation over asymmetric spectra

Disclosed is a system and method for signal conditioning and equalization in the time domain, preferably in a discrete multi-tone (DMT) modem. The system preferably includes a processor operating according to operating logic stored on a memory although a dedicated logical circuit may be employed. The operating logic includes logic executing the function of a low pass filter having a predetermined cutoff frequency configured to process a digitized data signal having a first sample rate f , producing a filtered data signal at a second sample rate f . The operating logic further includes logic which executes the function of a time domain equalizer, the time domain equalizer being configured to process the filtered signal to shorten the impulse response of the channel while at the same time, the time domain equalizer down-samples the filtered signal from the second sample rate f , to a third sample rate f for further processing in the frequency domain.

System and method for performing time domain equalization

A system and method are disclosed for synchronizing a predetermined repeated data sequence contained in a first data signal at a first sample rate with the same predetermined repeated data sequence contained in a second data signal at a second sample rate in a data communications device. The system preferably includes a digital signal processor operating pursuant to logic stored on a memory. The logic includes synchronization logic which reduces the first sample rate to a predetermined correlation sample rate using a first decimator, resulting in a first reduced data signal. The synchronization logic also reduces the second sample rate to the same predetermined correlation sample rate using a second decimator, resulting in a second reduced data signal. Finally, the synchronization logic determines a sequence offset between the predetermined repeated data sequence contained in the first reduced data signal and the predetermined repeated data sequence contained in the second reduced data signal using a correlator. This sequence offset is used to determine a time delay that is applied to the second data signal, thereby synchronizing the predetermined repeated data sequence contained in the first and second data sequences.

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Aberdeen, NJ, United States of America

Weimin Liu